XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 204

• Manufacturer Part Number: XC5VLX50-1FFG676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5: Configurable Logic Blocks (CLBs)
204
Slice Distributed RAM Timing Model and Parameters (Available in
SLICEM only)
Figure 5-27
slice. Some elements of the slice are omitted for clarity. Only the elements relevant to the
timing paths described in this section are shown.
X-Ref Target - Figure 5-27
Figure 5-27: Simplified Virtex-5 FPGA SLICEM Distributed RAM
illustrates the details of distributed RAM implemented in a Virtex-5 FPGA
D input
C input
B input
A input
CLK
WE
DX
CX
BX
AX
DI
CI
BI
AI
www.xilinx.com
6
6
6
6
DI1
DI2
A[6:0]
WA[6:0]
CLK
WE
DI1
DI2
A[6:0]
WA[6:0]
CLK
WE
DI1
DI2
A[6:0]
WA[6:0]
CLK
WE
DI1
DI2
A[6:0]
WA[6:0]
CLK
WE
RAM
RAM
RAM
RAM
O6
O5
O6
O5
O6
O5
O6
O5
UG190_5_27_050506
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
D
DMUX
C
CMUX
B
BMUX
A
AMUX