XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 307

• Manufacturer Part Number: XC5VLX50-1FFG676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Nominal SSO Limit
Table 6-40
outputs allowed per bank to avoid the effects of ground bounce.
Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank
Voltage
1.2V
provides the guidelines for the maximum number of simultaneously switching
HSTL_I_12
LVCMOS12_2_slow
LVCMOS12_4_slow
LVCMOS12_6_slow
LVCMOS12_8_slow
LVCMOS12_2_fast
LVCMOS12_4_fast
LVCMOS12_6_fast
LVCMOS12_8_fast
IOSTANDARD
www.xilinx.com
Limit per 20-pin Bank
Simultaneous Switching Output Limits
20
20
20
20
20
20
20
20
20
Limit per 40-pin Bank
40
40
40
40
40
40
40
40
40
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