XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 136

• Manufacturer Part Number: XC5VLX50-1FFG676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Block RAM
136
Block RAM Timing Characteristics
Clock Event 1
The timing diagram in
without the optional output register. The timing for read-first and no-change modes are
similar. For timing using the optional output register, an additional clock latency appears
at the DO pin. These waveforms correspond to latch mode when the optional output
pipeline register is not used.
X-Ref Target - Figure 4-14
At time 0, the block RAM is disabled; EN (enable) is Low.
Read Operation
During a read operation, the contents of the memory at the address on the ADDR inputs
remain unchanged.
•
•
•
•
ADDR
** SRVAL = 0101
SSR
CLK
* Write Mode = "WRITE_FIRST"
WE
DO
T
the block RAM.
At time T
block RAM, enabling the memory for the READ operation that follows.
At time T
become stable at the DO pins of the block RAM.
Whenever EN is asserted, all address changes must meet the specified setup and hold
window. Asynchronous address changes can affect the memory content and block
RAM functionality in an unpredictable way.
EN
DI
RCCK_ADDR
Disabled
RCCK_EN
RCKO_DO
1
T RDCK_DI
T RCCK_ADDR
T RCCK_EN
T RCCK_WE
DDDD
before clock event 1, address 00 becomes valid at the ADDR inputs of
00
T RCKO_DO
Read
MEM (00)
Figure 4-14: Block RAM Timing Diagram
before clock event 1, enable is asserted High at the EN input of the
Figure 4-14
after clock event 1, the contents of the memory at address 00
www.xilinx.com
2
CCCC
0F
describes a single-port block RAM in write-first mode
Write
CCCC*
3
T RCCK_SSR
BBBB
7E
Read
MEM (7E)
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
AAAA
8F
Reset
0101**
ug190_4_13_022207
5
0000
Disabled
20