XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 222

• Manufacturer Part Number: XC5VLX50-1FFG676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6: SelectIO Resources
222
X-Ref Target - Figure 6-5
The guidelines when using DCI cascading are as follows:
•
•
•
•
•
The master and slave banks must all reside on the same column (left, center, or right)
on the device.
Master and slave banks must have the same V
DCI I/O banking compatibility rules must be satisfied across all master and slave
banks (for example, only one DCI I/O standard using single termination type is
allowed across all master and slave banks). DCI I/O standard compatibility is not
constrained to one bank when DCI cascading is implemented; it extends across all
master and slave banks.
DCI cascading can span the entire column as long as the above guidelines are met.
Locate adjacent banks. Bank location information is best determined from partgen
generated package files (partgen -v XC5VLX50TFF1136). The resulting package
file with a .pkg extension contains XY I/O location information. The X designator
indicates I/Os in the same column. The Y designator indicates the position of an I/O
within a specific bank. The bank number is also shown. Consecutive Y locations
across bank boundaries show adjacent banks. For example, the XC5VLXT in an
FF1136 package shows bank 11 starting with I/O X0Y159 end ending with I/O
location X0Y120. Bank 13 starts with I/O X0Y119 and ends with X0Y80. Bank 15 starts
Local
Local
Local
Bank
Bank
Bank
To
To
To
(When Cascaded)
(When Cascaded)
To Banks Above
To Banks Below
Figure 6-5: DCI Cascading Supported Over Multiple Banks
www.xilinx.com
DCI
CCO
and V
REF
VRN/VRP
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
(if applicable) voltage.
UG190_6_96_012907
Bank A
Bank B
Bank C