IDT92HD81B1X5NLGXYCX8 IDT, Integrated Device Technology Inc, IDT92HD81B1X5NLGXYCX8 Datasheet - Page 35

• Manufacturer Part Number: IDT92HD81B1X5NLGXYCX8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT92HD81B1X5NLGXYCX8

• Lead Free Status / RoHS Status: Compliant

92HD81
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
IDT™ CONFIDENTIAL
2.20. HD Audio ECR 15b support
2.21. Digital Core Voltage Regulator
Although ECR15b is not yet complete (not a DCN), the 92HD81 will implement complete support for
the specification building on the support already present in previous products. ECR 15b features
supported are:
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The digital core operates from 1.4 to 1.98V making it compatible with 1.5V (5%) and 1.8V (10%) sup-
ply voltages. Many systems require that the CODEC use a single 3.3V digital supply, so an inte-
grated regulator is included on die. (Parts may be ordered with the regulator disabled). The regulator
uses pin 9, DVDD, as its voltage source. The output of the LDO is connected to pin 1 and the digital
core. A 10uF capacitor must be placed on pin 1 for proper load regulation and regulator stability.
The digital core voltage regulator is only dependent on DVDD. DVDDIO may be either 3.3 or 1.5V
and may proceed or follow DVDD in sequence. The CODEC digital logic and I/O (unless referenced
to AVDD) will operate in the absence of AVDD. DVDD and AVDD supply sequencing for the applica-
tion of power and the removal of power is neither defined nor guaranteed. It is common for desktop
systems to supply AVDD from the system standby supply and the CODEC will tolerate, indefinitely,
the condition where AVDD is active but DVDD and DVDDIO are inactive.
To prevent pops, software is expected to mute paths as close to the port as is possible when chang-
ing power states or signal topology.
Persistence of many configuration options through bus and function group reset.
The ability to support port presence detect in D3 even when the HD Audio bus is in a low power
state (no clock.)
Fast resume times from low power states: 1ms D1 to D0, 2ms D2 to D0, 10mS D3 to D0.
Notification if persistent register settings have been unexpectedly reset.
SPDIF active in D3 (required)
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92HD81