TMC22151KHC Fairchild Semiconductor, TMC22151KHC Datasheet - Page 66

• Manufacturer Part Number: TMC22151KHC
• Manufacturer: Fairchild Semiconductor

Specifications of TMC22151KHC

• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

TMC22x5y
Examples:
NTSC std with STS programmed to 858.
Base pixels per quadrant = Int(858/4) = 214
Pixel 0:
1. Pixel 0 <= 4*Int(858/4)
2. Required pixel 0 < 214 therefore quadrant = 0,
3. PG[10:0] = 511 - 214 + (0+[0*214]) = 297
Pixel 56:
1. Pixel 56 <= 4*Int(858/4)
2. Required pixel 56 < 214 therefore quadrant = 0
3. PG[10:0] = 511 - 214 + (56-[0*214]) = 353
Pixel 250:
1. Pixel 250 <= 4*Int(858/4)
2. Required pixel 250 > 214 therefore quadrant =/= 0
3. Required pixel 250 < 428 therefore quadrant = 1,
4. PG[10:0] = 1023 - 214 + (250-[1*214]) = 845
Pixel 800:
1. Pixel 800 <= 4*Int(858/4)
2. Required pixel 800 > 214 therefore quadrant =/= 0
3. Required pixel 800 > 428 therefore quadrant =/= 1
4. Required pixel 800 > 642 therefore quadrant =/= 2
5. Required pixel 800 < 858 therefore quadrant = 3,
6. PG[10:0]= 2047 - 214 + (800-[3*214]) = 1991
Pixel 856:
1. Pixel <= 4*Int(858/4)
2. Required pixel 856 > 214 therefore quadrant =/= 0
3. Required pixel 856 > 428 therefore quadrant =/= 1
4. Required pixel 856 > 642 therefore quadrant =/= 2
5. Required pixel 856 < 858 therefore quadrant = 3,
6. PG[10:>0] = 2047 - 214 + (856-[3*214]) = 2047
Pixel 857:
1. Pixel 857 > 4*Int(858/4)
2. Therefore quadrant = 3, [PG[10:9] = 11]
3. PG[10:0] = 1536 + (857-[4*214]) = 1537
Composite Line Grab
The composite line grab is only available in the 3 line comb
based decoders (TMC22053 and TMC22153), and allows
the user to grab any line from the 4 field sequence in NTSC
or 8 field sequence in PAL when LGEN is set HIGH. When
the LGEN register bit is set HIGH the decoder automatically
switches to operate as a “simple” bandsplit decoder. The
SET pin can also be used to produce the line grab pulse if
SET
Once the line grab has been activated the subcarrier oscilla-
tor is frozen with the SEED and phase from the beginning of
the line, and the composite video in the 1H line store is
frozen by disabling the write signals in LSTORE1. The read
66
2-0
[PG[10:9] = 00]
[PG[10:9] = 00]
[PG[10:9] = 01]
[PG[10:9] = 11]
[PG[10:9] = 11]
= 110 and LGEXT is set HIGH.
cycle for the frozen line store is still clocked by PCK. The
subcarrier DDS and the internal read only registers will be
updated once per clock period as normal, but will reload the
DRS SEED and PHASE values at the beginning of each line.
The G/Y, B/U, and R/V outputs will remain active, and the
DHSYNC and DVSYNC signals will remained locked to the
input or flywheel if the input has been removed.
The pixel grab function can be used in conjunction with the
frozen line to examine individual pixels inside the decoder.
Parallel Microprocessor Interface
The parallel microprocessor interface, active when SER is
HIGH, employs a 12-line interface, with an 8-bit data bus
and one address bit: two addresses are required for device
programming and pointer-register management. Address bit
0 selects between reading/writing the register addresses and
reading/writing register data. When writing, the address is
presented along with a LOW on the R/W pin during the fall-
ing edge of CS Eight bits of data are presented on D
ing the subsequent rising edge of CS. One additional falling
edge of CS is needed to move input data to its assigned
working registers.
In read mode, the address is accompanied by a HIGH on the
R/W pin during a falling edge of CS. The data output pins go
to a low-impedance state t
present on D
this port operates asynchronously with the pixel timing,
there is an uncertainty in this data valid output delay of one
PXCK period. This uncertainty does not apply to t
Writing data to specific control registers of the TMC22x5y
requires that the 8-bit address of the control register of inter-
est be written. This control register address is the base
address for subsequent write operations. The base address
autoincrements by one for each byte of data written after the
data byte intended for the base address. If more bytes are
transferred than there are available addresses, the address
will not increment and remain at its maximum value of 3Fh.
Table 24. Parallel Port Control
A
00
00
01
01
10
10
11
11
1-0
R/W
0
1
0
1
0
1
0
1
7-0
Load D
(block 00)
Read Control Register pointer on
D
Load D
Location pointer (block 01)
Read addressed XLUT Location pointer
on D
Write D
Register
Read addressed Control Register on
D
Write D
Read addressed XLUT Location on D
t
DOM
7-0
7-0
7-0
after the falling edge of CS. Because
7-0
7-0
7-0
7-0
.
DOZ
into Control Register pointer
into addressed XLUT
to addressed Control
to addressed XLUT Location
after CS falls. Valid data are
Action
PRODUCT SPECIFICATION
DOZ
7-0
.
dur-
7-0