TMC22151KHC Fairchild Semiconductor, TMC22151KHC Datasheet - Page 6

• Manufacturer Part Number: TMC22151KHC
• Manufacturer: Fairchild Semiconductor

Specifications of TMC22151KHC

• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

TMC22x5y
Pin Descriptions
6
Pin Name
Inputs
VIDEOA
VIDEOB
VSYNC
HSYNC
MASTER
BUFFER
CLOCK
SET
Outputs
G/Y
B/C
R/C
DVSYNC
DHSYNC
LDV
B9-0
9-0
R9-0
9-0
9-0
1-0
97, 98, 99, 100,
86, 85, 84, 83,
82, 81, 80, 79,
75, 74, 73, 72,
71, 70, 69, 68,
93, 94, 95, 96,
11, 12, 13, 14,
18, 19, 20, 21,
22, 23, 24, 25,
6, 7, 8, 9, 10,
Pin Number
78, 77
67, 66
88, 87
26, 27
1, 2
49
48
50
89
52
15
35
34
3
Value
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Pin Function Description
Video input A. An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205y) the data are left-justified (VIDEOA
Video input B. An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205y) the data are left-justified (VIDEOB
Vertical sync input. A vertical sync signal (active low) occurring at the
start of the first vertical sync pulse in a vertical field group. A falling edge
of VSYNC which is coincident with a falling edge of HSYNC indicates
field 1. This signal is active only when SPGIP
Horizontal sync input. A horizontal sync signal (active low) occurring
at the falling edge of the video sync. This signal is active only when
SPGIP
Master decoder control.
00
01
10
11
Control register select. This signal switches between two sets of
registers which control the gain or hue values in the output matrix.
When BUFFER = 0, registers 17-1F are active. When BUFFER = 1,
registers 27-2F take control.
Master processing clock. The clock signal can either be at twice the
pixel data rate in the line locked modes, or at four times the subcarrier
frequency in the subcarrier mode. The interpretation of the CLOCK
signal is set by the CKSEL register bit.
Programmable function pin. The function specified by the SET
register is active when SET is low. The decoder returns to its previous
operation when SET goes high.
Green or Luminance digital output. For 8-bit versions (TMC2205y)
the data are left-justified (G/Y
Blue or C
left-justified (B/C
Red or C
left-justified (R/C
Vertical sync output. The DVSYNC signal occurs once per field and
lasts for 1 video line.
Horizontal sync output. The DHSYNC signal occurs once per line and
lasts for 64 clock periods.
Data synchronization output. LDV can be an internally or externally
generated clock signal. The internal LDV signal is produced when the
CLOCK input is at twice the pixel data rate (PXCK); and is a pixel data
rate clock phase locked to the falling edge of the HSYNC. The external
LDV can be selected under software control, and must be at the
CLOCK, or a sub multiple of the CLOCK, frequency.
1-0
Adaptive comb decoder
Simple bandsplit decoder
Non adaptive comb filter
Flat notched luma and simple bandsplit chroma
R
B
= 00.
digital output. For 8-bit versions (TMC2205y) the data are
digital output. For 8-bit versions (TMC2205y) the data are
B 9-2
R 9-2
).
).
9-2
).
1-0
PRODUCT SPECIFICATION
= 00.
9-2
9-2
).
).