TMC22151KHC Fairchild Semiconductor, TMC22151KHC Datasheet - Page 65

• Manufacturer Part Number: TMC22151KHC
• Manufacturer: Fairchild Semiconductor

Specifications of TMC22151KHC

• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

PRODUCT SPECIFICATION
Table 23. Pixel Grab Control
If a single pixel every 4 fields in NTSC and 8 fields in PAL is
required to be grabbed, PGG and PGEN in register 30h
should be set HIGH. The pixel grab signal is the logical
AND of the GRABP, GRABL, and GRABF signals. GRABP
goes HIGH whenever the pixel count equals the programmed
pixel grab number, GRABL goes HIGH for one line when-
ever the line count equals the programmed line number,
and the GRABF goes HIGH for a field whenever the field
number equals the programmed field count.
If the same pixel on every line is required to be grabbed, then
PGG should be set LOW, which internally forces GRABL
and GRABF to be forced HIGH enabling the pixel grab
whenever GRABP goes HIGH.
LGEXT PGEN PGEXT LGEN
0
0
0
0
1
1
0
1
1
1
x
x
Pixel Count
Pixel Grab
GHSYNC
0
0
1
0
1
x
STS-1
STS-1
Figure 32: Relationship Between Pixel Count and Pixel Grab Value
0
1
0
0
0
1
x
x
x
x
GRABS = 0
GRABS =
PGRAB
GRABS = FGRAB
& LGRAB &
PGRAB
GRABS = NOT
(SET pin)
GRABS =
PGRAB
GRABS = NOT
(SET pin)
GRABS signal
Pixel Grab
value 0
28 pixels
The SET pin can be used to provide an external grab signal
when PGEXT is set HIGH in register 30h and the SET
function in register 00h, SET[2:0] is programmed to 110
(binary). In this mode the falling edge on the SET pin
triggers the pixel grab.
The GRABP, GRABL, and GRABF signals are available on
bits 0,1, and 2 respectively of the read only register 41. An
example of the pixel grab feature, would be grabbing a pixel
in the center of the burst period allowing the user to check
the burst height by reading the magnitude of the demodu-
lated U and V components. This would then allow the user to
compensate for any chrominance gain errors in the output
matrix.
The pixel grab value is delayed by 28 pixels from the pixel
count. This is the delay for all the pixel grab registers. Figure
32 shows this delay relative to GHSYNC. This means that if
28 is placed in the PG value, the actual pixel grabbed is
pixel 0.
The top two bits of the PG value provide the quadrant and
the bottom 9 bits provide the offset within that quadrant.
The integer part of STS/4 gives the maximum count for each
quadrant while the fractional result (bottom two bits)
provides the 0,1,2, or 3 count offset for the last quadrant.
For pixels value <= 4*Int(STS/4)
PG[10:9] = quadrant number
PG[8:0] = max quadrant count - Int(STS/4) + pixel offset
For pixels value > 4*Int(STS/4)
The quadrant is always number 3, ie PG[10:9] = 11 while the
pixel in excess of 4*Int(STS/4) is added to 1536.
Pixel 0
Pixel Grab
value 28
Pixel STS-1
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