ISP1504CBS,157 NXP Semiconductors, ISP1504CBS,157 Datasheet - Page 18
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ISP1504CBS,157
Manufacturer Part Number
ISP1504CBS,157
Description
RF Transceiver USB2.0 ULPI OTG
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1504ABS118.pdf
(83 pages)
Specifications of ISP1504CBS,157
Number Of Transceivers
1
Esd Protection
YeskV
Operating Supply Voltage (typ)
Not RequiredV
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
Not RequiredV
Operating Supply Voltage (min)
Not RequiredV
Pin Count
32
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Supply Voltage
1.65 V to 3.6 V
Mounting Style
SMD/SMT
Package / Case
HVQFN-32
Lead Free Status / RoHS Status
Compliant
Other names
935278309157 ISP1504CBS
NXP Semiconductors
Table 5.
Table 6.
ISP1504A_ISP1504C_3
Product data sheet
Signal
Reserved
INT
Reserved
Signal
TX_ENABLE
TX_DAT
TX_SE0
INT
RX_DP
RX_DM
RX_RCV
Reserved
Signal mapping during low-power mode
Signal mapping for 6-pin serial mode
8.1.3 6-pin full-speed or low-speed serial mode
8.1.4 3-pin full-speed or low-speed serial mode
Maps to
DATA2
DATA3
DATA[7:4]
Maps to
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1504 to 6-pin serial mode. In 6-pin serial mode, the DATA[7:0]
bus definition changes to that shown in
the 6PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 6-pin serial
mode, the link asserts STP. This is provided primarily for links that contain legacy
full-speed or low-speed functionality, providing a more cost-effective upgrade path to
high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1 .
If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1504 to 3-pin serial mode. In 3-pin serial mode, the data bus
definition changes to that shown in
3PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 3-pin serial
mode, the link asserts STP. This is primarily provided for links that contain legacy
full-speed or low-speed functionality, providing a more cost-effective upgrade path to
high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1 .
Direction
O
O
O
Direction
I
I
I
O
O
O
O
O
Description
reserved; the ISP1504 will drive this pin to LOW
active HIGH interrupt indication; will be asserted whenever any unmasked
interrupt occurs
reserved; the ISP1504 will drive these pins to LOW
Description
active HIGH transmit enable
transmit differential data on DP and DM
transmit single-ended zero on DP and DM
active HIGH interrupt indication; will be asserted whenever any
unmasked interrupt occurs
single-ended receive data from DP
single-ended receive data from DM
differential receive data from DP and DM
reserved; the ISP1504 will drive this pin to LOW
Rev. 03 — 7 April 2008
…continued
Table
Table
7. To enter 3-pin serial mode, the link sets the
ISP1504A; ISP1504C
6. To enter 6-pin serial mode, the link sets
ULPI HS USB OTG transceiver
© NXP B.V. 2008. All rights reserved.
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