ISP1504CBS,157 NXP Semiconductors, ISP1504CBS,157 Datasheet - Page 16
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ISP1504CBS,157
Manufacturer Part Number
ISP1504CBS,157
Description
RF Transceiver USB2.0 ULPI OTG
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1504ABS118.pdf
(83 pages)
Specifications of ISP1504CBS,157
Number Of Transceivers
1
Esd Protection
YeskV
Operating Supply Voltage (typ)
Not RequiredV
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
Not RequiredV
Operating Supply Voltage (min)
Not RequiredV
Pin Count
32
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Supply Voltage
1.65 V to 3.6 V
Mounting Style
SMD/SMT
Package / Case
HVQFN-32
Lead Free Status / RoHS Status
Compliant
Other names
935278309157 ISP1504CBS
NXP Semiconductors
8. Modes of operation
ISP1504A_ISP1504C_3
Product data sheet
8.1.1 Synchronous mode
8.1 ULPI modes
The ISP1504 ULPI bus can be programmed to operate in four modes. Each mode
reconfigures the signals on the data bus as described in the following subsections. Setting
more than one mode will lead to undefined behavior.
This is default mode. At power-up, and when CLOCK is stable, the ISP1504 will enter
synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the
set-up and hold times as defined in
synchronous mode is given in
This mode is used by the link to perform the following tasks:
For more information on various synchronous mode protocols, see
Table 4.
Signal
name
CLOCK
DATA[7:0] I/O
•
•
•
•
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RXCMDs)
ULPI signal description
Direction
on ISP1504
O
Rev. 03 — 7 April 2008
Signal description
60 MHz interface clock. If a crystal is attached or a clock is driven into
the XTAL1 pin, the ISP1504 will drive a 60 MHz output clock.
8-bit data bus. In synchronous mode, the link drives DATA[7:0] to LOW
by default. The link initiates transfers by sending a nonzero data pattern
called TXCMD (transmit command). In synchronous mode, the direction
of DATA[7:0] is controlled by DIR. Contents of DATA[7:0] lines must be
ignored for exactly one clock cycle whenever DIR changes value. This is
called the turnaround cycle.
Data lines have fixed direction and different meaning in low-power and
serial modes.
Table
Section
4.
15. A description of the ULPI pin behavior in
ISP1504A; ISP1504C
ULPI HS USB OTG transceiver
Section
© NXP B.V. 2008. All rights reserved.
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