PIC32MX110F016B-I/SS Microchip Technology, PIC32MX110F016B-I/SS Datasheet - Page 35

• Manufacturer Part Number: PIC32MX110F016B-I/SS
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, CTMU, 4 DMA 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the pri-
mary register file instead of the HI/LO register pair. By
avoiding the explicit MFLO instruction required when
using the LO register, and by supporting multiple desti-
nation registers, the throughput of multiply-intensive
operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
TABLE 3-2:
© 2011 Microchip Technology Inc.
Note 1:
Register
Number
17-22
25-29
0-6
10
11
12
12
12
12
13
14
15
15
16
16
16
16
23
24
30
31
7
8
9
2:
Registers used in exception processing.
Registers used during debug.
Reserved
HWREna
BadVAddr
Count
Reserved
Compare
Status
IntCtl
SRSCtl
SRSMap
Cause
EPC
PRId
EBASE
Config
Config1
Config2
Config3
Reserved
Debug
DEPC
Reserved
ErrorEPC
DESAVE
(1)
(1)
Register
(1)
COPROCESSOR 0 REGISTERS
(1)
(2)
(1)
(2)
Name
(1)
(1)
(2)
(1)
(1)
(1)
Reserved in the PIC32MX1XX/2XX family core.
Enables access via the RDHWR instruction to selected hardware registers.
Reports the address for the most recent address-related exception.
Processor cycle count.
Reserved in the PIC32MX1XX/2XX family core.
Timer interrupt control.
Processor status and control.
Interrupt system status and control.
Shadow register set status and control.
Provides mapping from vectored interrupt to a shadow set.
Cause of last general exception.
Program counter at last exception.
Processor identification and revision.
Exception vector base register.
Configuration register.
Configuration Register 1.
Configuration Register 2.
Configuration Register 3.
Reserved in the PIC32MX1XX/2XX family core.
Debug control and exception status.
Program counter at last debug exception.
Reserved in the PIC32MX1XX/2XX family core.
Program counter at last error.
Debug handler scratchpad register.
Preliminary
3.2.3
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configura-
tion information, such as presence of options like
MIPS16e, is also available by accessing the CP0
registers, listed in
Function
SYSTEM CONTROL
COPROCESSOR (CP0)
PIC32MX1XX/2XX
Table
3-2.
DS61168C-page 35