PIC32MX110F016B-I/SS Microchip Technology, PIC32MX110F016B-I/SS Datasheet - Page 176

• Manufacturer Part Number: PIC32MX110F016B-I/SS
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, CTMU, 4 DMA 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 17-1:
DS61168C-page 176
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
GCEN: General Call Enable bit (when operating as I
1 = Enable interrupt when a general call address is received in the I2CxRSR
0 = General call address disabled
STREN: SCLx Clock Stretch Enable bit (when operating as I
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
ACKDT: Acknowledge Data bit (when operating as I
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
0 = Acknowledge sequence not in progress
RCEN: Receive Enable bit (when operating as I
1 = Enables Receive mode for I
0 = Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
0 = Repeated Start condition not in progress
SEN: Start Condition Enable bit (when operating as I
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start condition not in progress
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
(module is enabled for reception)
Hardware clear at end of master Acknowledge sequence.
master Repeated Start sequence.
I2C
X
CON: I
2
C master, applicable during master receive)
2
C™ CONTROL REGISTER (CONTINUED)
2
C. Hardware clear at end of eighth bit of master receive data byte.
Preliminary
2
C master)
2
2
2
2
C master, applicable during master receive)
C slave)
C master)
C master)
2
C slave)
2
C master)
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