PIC32MX110F016B-I/SS Microchip Technology, PIC32MX110F016B-I/SS Datasheet - Page 175

• Manufacturer Part Number: PIC32MX110F016B-I/SS
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, CTMU, 4 DMA 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

REGISTER 17-1:
© 2011 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Note 1:
Range
31:24
23:16
15:8
Bit
7:0
ON: I
1 = Enables the I
0 = Disables the I
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
SCLREL: SCLx Release Control bit (when operating as I
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at
beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
STRICT: Strict I
1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate
0 = Strict I
A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
31/23/15/7
GCEN
ON
R/W-0
R/W-0
addresses in reserved address space.
Bit
U-0
U-0
—
—
2
C Enable bit
(1)
2
I2C
C Reserved Address Rule not enabled
30/22/14/6
X
2
C Reserved Address Rule Enable bit
STREN
CON: I
2
R/W-0
2
(1)
C module and configures the SDA and SCL pins as serial port pins
Bit
U-0
U-0
U-0
C module; all I
—
—
—
2
C™ CONTROL REGISTER
HC = Cleared in Hardware
W = Writable bit
‘1’ = Bit is set
29/21/13/5
ACKDT
R/W-0
SIDL
R/W-0
Bit
U-0
U-0
—
—
2
C pins are controlled by PORT functions
Preliminary
28/20/12/4
SCLREL
R/W-1, HC
R/W-0, HC
ACKEN
Bit
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
R/W-0, HC
STRICT
2
RCEN
C slave)
R/W-0
Bit
U-0
U-0
—
—
PIC32MX1XX/2XX
26/18/10/2
R/W-0, HC
A10M
R/W-0
PEN
Bit
U-0
U-0
—
—
x = Bit is unknown
25/17/9/1
DISSLW
R/W-0, HC
RSEN
R/W-0
Bit
U-0
U-0
—
—
DS61168C-page 175
24/16/8/0
R/W-0, HC
SMEN
R/W-0
SEN
Bit
U-0
U-0
—
—