PIC32MX110F016B-I/SS Microchip Technology, PIC32MX110F016B-I/SS Datasheet - Page 195

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PIC32MX110F016B-I/SS

Manufacturer Part Number
PIC32MX110F016B-I/SS
Description
PIC32, 16KB Flash, 4KB RAM, 40 MHz, CTMU, 4 DMA 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Datasheet
REGISTER 20-1:
© 2011 Microchip Technology Inc.
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
4:
5:
6:
RTCWREN: RTC Value Registers Write Enable bit
1 = RTC Value registers can be written to by the user
0 = RTC Value registers are locked out from being written to by the user
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read
0 = RTC Value registers can be read without concern about a rollover ripple
HALFSEC: Half-Second Status bit
1 = Second half period of a second
0 = First half period of a second
RTCOE: RTCC Output Enable bit
1 = RTCC clock output enabled – clock presented onto an I/O
0 = RTCC clock output disabled
This register is reset only on a Power-on Reset (POR).
The ON bit is only writable when RTCWREN = 1.
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
If the register is read twice and results in the same data, the data can be assumed to be valid
RTCCON: RTC CONTROL REGISTER
(6)
Preliminary
(5)
(1)
(CONTINUED)
PIC32MX1XX/2XX
DS61168C-page 195

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