PIC32MX110F016B-I/SS Microchip Technology, PIC32MX110F016B-I/SS Datasheet - Page 108

• Manufacturer Part Number: PIC32MX110F016B-I/SS
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, CTMU, 4 DMA 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 9-4:
DS61168C-page 108
Legend:
R = Readable bit
-n = Value at POR
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits
bit 27
bit 26-25 Unimplemented: Read as ‘0’
bit 24
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8
bit 7
Note 1:
Range
31:24
23:16
15:8
Bit
7:0
11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order
10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per
01 = Endian byte swap on word boundaries (i.e., reverse source byte order)
00 = No swapping (i.e., source byte order)
WBO: CRC Write Byte Order Selection bit
1 = Source data is written to the destination re-ordered as defined by BYTO<1:0>
0 = Source data is written to the destination unaltered
BITO: CRC Bit Order Selection bit
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)
0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected)
0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)
PLEN<4:0>: Polynomial Length bits
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
These bits are unused.
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Denotes the length of the polynomial – 1.
CRCEN: CRC Enable bit
1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
31/23/15/7
CRCEN
R/W-0
Bit
U-0
U-0
U-0
—
—
—
per half-word)
half-word)
DCRCCON: DMA CRC CONTROL REGISTER
CRCAPP
30/22/14/6
R/W-0
Bit
U-0
U-0
U-0
—
—
—
(1)
W = Writable bit
‘1’ = Bit is set
29/21/13/5
CRCTYP
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(4)
BYTO<1:0>
(1)
Preliminary
28/20/12/4
(1)
R/W-0
R/W-0
Bit
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
WBO
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(1)
PLEN<4:0>
26/18/10/2
R/W-0
R/W-0
Bit
U-0
U-0
—
—
© 2011 Microchip Technology Inc.
CRCCH<2:0>
x = Bit is unknown
25/17/9/1
R/W-0
R/W-0
Bit
U-0
U-0
—
—
24/16/8/0
BITO
R/W-0
R/W-0
R/W-0
Bit
U-0
—