PIC24HJ32GP202-E/MM Microchip Technology, PIC24HJ32GP202-E/MM Datasheet - Page 266

• Manufacturer Part Number: PIC24HJ32GP202-E/MM
• Description: 16-bit MCU, 32KB Flash,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ32GP202-E/MM

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24HJ32GP202/204 AND PIC24HJ16GP304
Instruction Addressing Modes............................................. 40
Instruction Set
Instruction-Based Power-Saving Modes ............................. 99
Internal RC Oscillator
Internet Address................................................................ 257
Interrupt Control and Status Registers................................ 65
Interrupt Setup Procedures ................................................. 87
Interrupt Vector Table (IVT) ................................................ 61
Interrupts Coincident with Power Save Instructions.......... 100
J
JTAG Boundary Scan Interface ........................................ 171
M
Memory Organization.......................................................... 25
Microchip Internet Web Site .............................................. 257
MPLAB ASM30 Assembler, Linker, Librarian ................... 188
MPLAB Integrated Development Environment Software .. 187
MPLAB PM3 Device Programmer..................................... 190
MPLAB REAL ICE In-Circuit Emulator System................. 189
MPLINK Object Linker/MPLIB Object Librarian ................ 188
Multi-Bit Data Shifter ........................................................... 24
N
NVM Module
O
Open-Drain Configuration ................................................. 104
Output Compare................................................................ 133
P
Packaging ......................................................................... 235
Peripheral Module Disable (PMD)..................................... 100
Pinout I/O Descriptions (table) ............................................ 13
PMD Module
PORTA
PORTB
Power-on Reset (POR) ....................................................... 58
Power-Saving Features....................................................... 99
DS70289G-page 266
File Register Instructions ............................................ 40
Fundamental Modes Supported.................................. 41
MCU Instructions ........................................................ 40
Move and Accumulator Instructions ............................ 41
Other Instructions........................................................ 41
Overview ................................................................... 181
Summary................................................................... 179
Idle ............................................................................ 100
Sleep ........................................................................... 99
Use with WDT ........................................................... 175
IECx ............................................................................ 65
IFSx............................................................................. 65
INTCON1 .................................................................... 65
INTCON2 .................................................................... 65
IPCx ............................................................................ 65
Initialization ................................................................. 87
Interrupt Disable.......................................................... 87
Interrupt Service Routine ............................................ 87
Trap Service Routine .................................................. 87
Register Map............................................................... 39
Registers ................................................................... 135
Details ....................................................................... 236
Marking ..................................................................... 235
Register Map............................................................... 39
Register Map............................................................... 38
Register Map............................................................... 38
Clock Frequency and Switching.................................. 99
Program Address Space..................................................... 25
Program Memory
R
Reader Response............................................................. 258
Registers
Construction ............................................................... 42
Data Access from Program Memory Using Program
Data Access from Program Memory Using Table Instruc-
Data Access from, Address Generation ..................... 43
Memory Map............................................................... 25
Table Read Instructions
Visibility Operation ...................................................... 45
Interrupt Vector ........................................................... 26
Organization ............................................................... 26
Reset Vector ............................................................... 26
AD1CHS0 (ADC1 Input Channel 0 Select ................ 167
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 165
AD1CON1 (ADC1 Control 1) .................................... 161
AD1CON2 (ADC1 Control 2) .................................... 163
AD1CON3 (ADC1 Control 3) .................................... 164
AD1CSSL (ADC1 Input Scan Select Low)................ 169
AD1PCFGL (ADC1 Port Configuration Low) ............ 169
CLKDIV (Clock Divisor) .............................................. 94
CORCON (Core Control) ...................................... 23, 67
I2CxCON (I2Cx Control) ........................................... 145
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 149
I2CxSTAT (I2Cx Status) ........................................... 147
ICxCON (Input Capture x Control)............................ 132
IEC0 (Interrupt Enable Control 0) ......................... 74, 77
IEC1 (Interrupt Enable Control 1) ............................... 76
IFS0 (Interrupt Flag Status 0) ..................................... 70
IFS1 (Interrupt Flag Status 1) ..................................... 72
IFS4 (Interrupt Flag Status 4) ..................................... 73
INTCON1 (Interrupt Control 1).................................... 68
INTCON2 (Interrupt Control 2).................................... 69
INTTREG Interrupt Control and Status Register ........ 86
IPC0 (Interrupt Priority Control 0) ............................... 78
IPC1 (Interrupt Priority Control 1) ............................... 79
IPC16 (Interrupt Priority Control 16) ........................... 85
IPC2 (Interrupt Priority Control 2) ............................... 80
IPC3 (Interrupt Priority Control 3) ............................... 81
IPC4 (Interrupt Priority Control 4) ............................... 82
IPC5 (Interrupt Priority Control 5) ............................... 83
IPC7 (Interrupt Priority Control 7) ............................... 84
NVMCOM (Flash Memory Control)....................... 49, 50
OCxCON (Output Compare x Control) ..................... 135
OSCCON (Oscillator Control) ..................................... 92
OSCTUN (FRC Oscillator Tuning).............................. 96
PLLFBD (PLL Feedback Divisor)................................ 95
PMD1 (Peripheral Module Disable Control
PMD2 (Peripheral Module Disable Control
RCON (Reset Control)................................................ 54
SPIxCON1 (SPIx Control 1)...................................... 139
SPIxCON2 (SPIx Control 2)...................................... 141
SPIxSTAT (SPIx Status and Control) ....................... 138
SR (CPU Status)................................................... 22, 66
T1CON (Timer1 Control) .......................................... 124
TxCON (T2CON, T4CON, T6CON or
Space Visibility ................................................... 45
tions .................................................................... 44
TBLRDH ............................................................. 44
TBLRDL.............................................................. 44
Register 1) ........................................................ 101
Register 2) ........................................................ 102
T8CON Control)................................................ 128
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