PIC24HJ32GP202-E/MM Microchip Technology, PIC24HJ32GP202-E/MM Datasheet - Page 171

• Manufacturer Part Number: PIC24HJ32GP202-E/MM
• Description: 16-bit MCU, 32KB Flash,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ32GP202-E/MM

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.0
PIC24HJ32GP202/204
devices include several features that are intended to
maximize application flexibility and reliability, and
minimize
components. These are:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
TABLE 19-1:
© 2011 Microchip Technology Inc.
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A
0xF8000C FPOR
0xF8000E
0xF80010
0xF80012
0xF80014
0xF80016
Legend: — = unimplemented bit, read as ‘0’.
Note 1:
Note:
Address
2:
SPECIAL FEATURES
PIC24HJ32GP202/204 AND PIC24HJ16GP304
These bits are reserved and always read as ‘1’.
These bits are reserved for use by development tools and must be programmed as ‘1’.
cost
This data sheet summarizes the features
of
PIC24HJ16GP304 devices. It is not
intended
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F/PIC24H
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
dsPIC33F/PIC24H
Manual sections.
FBS
Reserved
FGS
FOSCSEL
FOSC
FWDT
FICD
FUID0
FUID1
FUID2
FUID3
Name
the
DEVICE CONFIGURATION REGISTER MAP
through
PIC24HJ32GP202/204
to
FWDTEN
and
be
elimination
IESO
Bit 7
FCKSM<1:0>
—
—
—
Reserved
Family
Family
a
PIC24HJ16GP304
Reserved
comprehensive
WINDIS
(2)
Bit 6
of
—
—
—
—
Reference
Reference
external
(1)
and
IOL1WAY
JTAGEN
Bit 5
—
—
—
—
—
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
19.1
PIC24HJ32GP202/204
devices provide nonvolatile memory implementation
for device configuration bits. Refer to Section 25.
“Device
“dsPIC33F/PIC24H Family Reference Manual”, for
more information on this implementation.
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The Device Configuration register map is shown in
Table
The individual Configuration bit descriptions for the
Configuration registers are shown in
Note that address 0xF80000 is beyond the user
program memory space. It belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using table reads and table writes.
WDTPRE
ALTI2C
Bit 4
—
—
—
—
—
19-1.
Configuration Bits
—
Configuration”
Bit 3
—
—
—
—
—
BSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
Bit 2
and
—
—
GSS<1:0>
(DS70194)
FPWRT<2:0>
FNOSC<2:0>
DS70289G-page 171
PIC24HJ16GP304
Table
Bit 1
—
ICS<1:0>
19-2.
of
GWRP
BWRP
Bit 0
—
the