PIC18LF13K50T-I/SS Microchip Technology, PIC18LF13K50T-I/SS Datasheet - Page 26

• Manufacturer Part Number: PIC18LF13K50T-I/SS
• Description: 8 KB Flash, 512 RAM, 15 I/O, 10-bit ADC, USB 2.0, NanoWatt XLP 20 SSOP .209in T/
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K50T-I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F1XK50/PIC18LF1XK50
FIGURE 5-4:
FIGURE 5-5:
5.5
A data EEPROM address may be read via a sequence
of core instructions (4-bit command, ‘0000’) and then
output on PGD via the 4-bit command, ‘0010’ (TABLAT
register). The result may then be immediately
compared to the appropriate data in the programmer’s
memory for verification. Refer to Section 5.4 “Read
Data EEPROM Memory” for implementation details of
reading data EEPROM.
DS41342E-page 26
PGC
PGD
Note 1:
PGC
PGD
Verify Data EEPROM
1
0
2
1
Magnification of the High-Impedance delay between PGC and PGD is shown in Figure 5-5.
MSb
3
0
4
0
SHIFT OUT DATA HOLDING REGISTER TIMING DIAGRAM (0010)
HIGH-IMPEDANCE DELAY
P5
PGD = Input
1
1
n
P19
2
P3
3
2
4
n
5
Advance Information
6
7
8
P6
9
LSb
P14
5.6
The term “Blank Check” means to verify that the device
has no programmed memory cells. All memories must
be verified: program Flash, data EEPROM, ID locations
and Configuration bits. The device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” memory cell will read as a ‘1’.
Therefore, Blank Checking a device merely means to
verify that all bytes read as FFh except the
Configuration bits. Unused (reserved) Configuration
bits will read ‘0’ (programmed). Refer to Table 6-1 for
blank configuration expect data for the various
PIC18F1XK50/PIC18LF1XK50 devices.
Given that Blank Checking is merely code and data
EEPROM verification with FFh expect data, refer to
Section 5.4 “Read Data EEPROM Memory” and
Section 5.2 “Verify Program Flash and ID Locations”
for implementation details.
FIGURE 5-6:
10 11
1
2
PGD = Output
12
Shift Data Out
Blank Check
3
Blank Check Device
13
4
14
device
blank?
Abort
5
Start
Is
15 16
No
6
BLANK CHECK FLOW
 2010 Microchip Technology Inc.
MSb
P5A
(Note 1)
(Note 1)
Fetch Next 4-bit Command
Yes
1
n
PGD = Input
2
n
Continue
3
n
4
n