PIC18LF13K50T-I/SS Microchip Technology, PIC18LF13K50T-I/SS Datasheet
PIC18LF13K50T-I/SS
Specifications of PIC18LF13K50T-I/SS
Related parts for PIC18LF13K50T-I/SS
PIC18LF13K50T-I/SS Summary of contents
Page 1
... Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 operate from 1.8 to 3.6 volts. All other aspects of the PIC18F1XK50 with regards to the PIC18LF1XK50 programming devices are identical. 2.1 Hardware Requirements In High-Voltage ICSP mode, the PIC18F1XK50/ PIC18LF1XK50 devices require two programmable power supplies: one for V RA3. Both supplies should have a minimum resolution of 0.25V. Refer to Section 8.1 “ ...
Page 2
... PIC18F1XK50/PIC18LF1XK50 FIGURE 2-2: IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) PIC18LF1XK50 RECOMMENDED CIRCUIT Application 1 10K 0.1 FIGURE 2-3: OUT OF CIRCUIT PROGRAMMING DS41342E-page 2 Programmer MCLR 330 MCLR USB Advance Information ICSPDAT ICSPCLK ICSPDAT ICSPCLK 2010 Microchip Technology Inc. ...
Page 3
... Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying V IHH V /RA3 pin While in Low-Voltage ICSP mode, the RC3 pin can no longer be used as a general purpose I/O. 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 ICSP . IHH to the MCLR/ Advance Information DS41342E-page 3 ...
Page 4
... Low-Voltage ICSP™ input when LVP Configuration bit equals ‘1’ I Serial Clock I/O Serial Data ) pins must be connected RA0/D+/PGD 3 18 RA1/D-/PGC USB 5 16 RC0/AN4/C12IN+/INT0 RC1/AN5/C12IN1-/INT1 RC2/AN6/P1D/C12IN2-/CV 8 RB4/AN10/SDI/SDA RB5/AN11/RX/DT 10 RB6/SCK/SCL 11 Advance Information (1) during programming. + REF - REF /INT2 REF 2010 Microchip Technology Inc. ...
Page 5
... FIGURE 2-5: 20-PIN QFN PIN DIAGRAMS FOR PIC18F1XK50 AND PIC18LF1XK50 20-Pin QFN 5x5 mm RA3/MCLR/V RC5/CCP1/P1A/T0CKI RC4/P1B/C12OUT/SRQ RC3/AN7/P1C/C12IN3-/PGM RC6/AN8/SS/T13CKI/T1OSCI 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 RA1/D-/PGC USB 3 13 RC0/AN4/C12IN+/INT0 RC1/AN1/C12IN1-/INT1 RC2/AN6/P1D/C12IN2-/ Advance Information + REF - REF /INT2 REF DS41342E-page 5 ...
Page 6
... Boot Block Boot Block* Block 0 Block 0 Block 1 Block 1 Unimplemented Unimplemented Read ‘0’s Read ‘0’s Advance Information Program Flash Size (Words) 000000h-000FFFh (4K) 000000h-001FFFh (8K) Address Range 000000h 0003FFh 000400h 0007FFh 000800h 000FFFh 001000h 001FFFh 002000h 00FFFFh 2010 Microchip Technology Inc. ...
Page 7
... Program Flash 00FFFFh Unimplemented Read as ‘0’ 100000h Configuration and ID Space 1FFFFFh Note 1: Boot Block size is determined by the BBSIZ bit in the CONFIG4L register. 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 MEMORY SIZE/DEVICE 4 KW (PIC18F13K50) BBSIZ = 1 BBSIZ = 0 Boot Block Boot Block* Block 0 Block 0 ...
Page 8
... ID Location 7 200006h ID Location 8 200007h CONFIG1L 300000h CONFIG1H 300001h CONFIG2L 300002h CONFIG2H 300003h 300004h CONFIG3H 300005h CONFIG4L 300006h 300007h CONFIG5L 300008h CONFIG5H 300009h CONFIG6L 30000Ah CONFIG6H 30000Bh CONFIG7L 30000Ch CONFIG7H 30000Dh Device ID1 3FFFFEh Device ID2 3FFFFFh 2010 Microchip Technology Inc. ...
Page 9
... Verify IDs Verify Data Program Configuration Bits Verify Configuration Bits Done 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 3.3 Entering and Exiting High-Voltage ICSP Program/Verify Mode As shown in Figure 3-6, the High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and then raising MCLR/V (high voltage) ...
Page 10
... ENTERING LOW-VOLTAGE PROGRAM/VERIFY MODE P15 P12 V IH MCLR/V /RA3 PGM PGD PGC PGD = Input DS41342E-page 10 FIGURE 3-9: MCLR/V /RA3 PGM PGD PGC is ‘1’ (see /RA3 Advance Information EXITING LOW-VOLTAGE PROGRAM/VERIFY MODE P16 P18 PGD = Input 2010 Microchip Technology Inc. ...
Page 11
... P4 P3 PGD 4-bit Command 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 3.5.2 CORE INSTRUCTION The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to set up registers as appropriate for use with other commands. TABLE 3-2: Core Instruction (Shift in16-bit instruction) ...
Page 12
... MOVWF TBLPTRL 6E F6 Write 8F8Fh TO 3C0004h erase entire device. NOP 00 00 Hold PGD low until erase 00 00 completes. BULK ERASE FLOW Start Write 0F0Fh to 3C0005h Write 8F8Fh to 3C0004h to Erase Entire Device Delay P11 + P10 Time Done 2010 Microchip Technology Inc. ...
Page 13
... Program Flash” determined that a data EEPROM erase must be performed at a supply voltage below the Bulk Erase limit, follow the methodology described in Section 4.3 “Data EEPROM Programming” and write ‘1’s to the array. 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 ...
Page 14
... BSF EECON1, WREN CLRF TBLPTRU CLRF TBLPTRH CLRF TBLPTRL BSF EECON1, FREE BSF EECON1, WR NOP NOP Erase starts on the 4th clock of this instruction MOVF EECON1 MOVWF TABLAT NOP (1) Shift out data BCF EECON1, WREN Advance Information 2010 Microchip Technology Inc. ...
Page 15
... FIGURE 4-3: SINGLE ROW ERASE PROGRAM FLASH FLOW Addr = Addr + 64 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Start Addr = 0 Configure Device for Row Erases Perform Erase Sequence No WR Bit Clear? Yes All No Rows done? Yes Done Advance Information DS41342E-page 15 ...
Page 16
... MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. Advance Information Erase Size (bytes) (bytes 2010 Microchip Technology Inc. ...
Page 17
... PGC P5 PGD 4-bit Command 16-bit Data Payload Note 1: Use P9A for Configuration Word programming. 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No bytes written? Yes Start Write Sequence and Hold PGC ...
Page 18
... TBLPTRL Write 2 bytes and post-increment address by 2. Repeat as many times as necessary to fill the write buffer Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. BCF EECON1, WREN Advance Information 2010 Microchip Technology Inc. ...
Page 19
... PGC PGD 4-bit Command BSF EECON1 PGC Poll WR bit PGD 4-bit Command 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 FIGURE 4-6: P5A P5A 2 NOP commands Poll WR bit, Repeat until Clear PGD = Input P5A 4-bit Command MOVWF TABLAT MOVF EECON1 PGD = Input Advance Information ...
Page 20
... MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH MOVLW <Data> MOVWF EEDATA BSF EECON1, WREN BSF EECON1, WR NOP NOP ;write starts on 4th clock of this instruction MOVF EECON1 MOVWF TABLAT NOP (1) Shift out data BCF EECON1, WREN Advance Information 2010 Microchip Technology Inc. ...
Page 21
... Boot Block Programming The code sequence detailed in Table 4-5 should be used, except that the address used in “Step 2” will be in the range of 000000h to 0007FFh. 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Table 4-8 demonstrates the code sequence, required to write the ID locations. In order to modify the ID locations, refer to the methodology described in Section 4.2.1 “ ...
Page 22
... MOVLW 01h MOVWF TBLPTRL Load 2 bytes and start programming. NOP - hold PGC high for time P9A and low for time P10. Load Odd Configuration Address Program Delay P9 and P10 Time for Write Advance Information Start MSB Done 2010 Microchip Technology Inc. ...
Page 23
... PGD = Input Note 1: Magnification of the high-impedance delay between PGC and PGD is shown in Figure 5-5. 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 The 4-bit command is shifted in LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of ...
Page 24
... Set TBLPTR = 200000h Increment Pointer Failure, Report Error No Advance Information Read Low Byte with Post-Increment Read High byte with Post-Increment Does No Word = Expect Failure, data? Report Error Yes All ID locations verified? Yes Done 2010 Microchip Technology Inc. ...
Page 25
... A8 0000 6E F5 0000 00 00 0000 <MSB><LSB> 0010 Note 1: The <LSB> is undefined. The <MSB> is the data. 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 FIGURE 5-3: Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH ...
Page 26
... Section 5.2 “Verify Program Flash and ID Locations” for implementation details. FIGURE 5-6: Blank Check Device Advance Information (Note P5A (Note MSb Fetch Next 4-bit Command PGD = Input BLANK CHECK FLOW Start Is Yes device Continue blank? No Abort 2010 Microchip Technology Inc. ...
Page 27
... DEVID registers are read-only and cannot be programmed by the user. 3: VREG is read-only. VREG = 1 for PIC18F1XK50 devices and VREG = 0 for PIC18LF1XK50 devices. The VREG bit value should not be included in any Verify or Checksum operation. 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 6.2 Device ID Word The ...
Page 28
... DEVICE ID VALUE Device PIC18LF13K50 PIC18LF14K50 PIC18F13K50 PIC18F14K50 Note: The ‘x’s in DEVID1 contain the device revision code. DS41342E-page 28 Device ID Value DEVID2 47h 47h 47h 47h Advance Information DEVID1 000x xxxx 001x xxxx 010x xxxx 011x xxxx 2010 Microchip Technology Inc. ...
Page 29
... FOSC<3:0> CONFIG1H BORV<1:0> CONFIG2L VREG CONFIG2L 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Description USB Clock Selection bit Selects the clock source for low-speed USB operation 1 = USB clock comes from the OSC1/OSC2 divided USB clock comes directly from the OSC1/OSC2 Oscillator block; no ...
Page 30
... Boot Block size for PIC18F14K50 (1 kW Boot Block size for PIC18F13K50 Boot Block size for PIC18F14K50 (512 W Boot Block size for PIC18F13K50) Low-Voltage Programming Enable bit 1 = Low-Voltage Programming enabled, RC3 is the PGM pin 0 = Low-Voltage Programming disabled, RC3 is an I/O pin Advance Information 2010 Microchip Technology Inc. ...
Page 31
... EBTRB CONFIG7H DEV<10:3> DEVID2 DEV<2:0> DEVID1 REV<4:0> DEVID1 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Description Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled Code Protection bits (Block 1 program Flash area Block 1 is not code-protected 0 = Block 1 is code-protected ...
Page 32
... An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the hex file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 7.2 Checksum Computation The checksum is calculated by summing the following: • ...
Page 33
... Legend: Item Description CONFIGx = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Checksum Advance Information 0xAA at 0 Blank and Max Value Address C2DB C231 ...
Page 34
... DD – DIS Advance Information + 0.3V) USB + 0.3V {( (V – 2010 Microchip Technology Inc. ...
Page 35
... T CY PWRT only) + 1.5 s (for EC mode only) where T and T is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device OSC data sheet for the particular device. 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Min. Max. 8 1.80 V 2.70 5 ...
Page 36
... Conditions — ms s — s — PIC18F1XK50 Only. Refer to Figure 2-1. — ns s — PIC18F1XK50 Only. Refer to Figure 2-1. — ns s — — — s — ; this can cause spurious program is the Power-up Timer period PWRT 2010 Microchip Technology Inc. ...
Page 37
... Updated to add V to Config 2L. Various minor edits. REG Revision C (January 2009) Updated to replace some data in Table 8.1. Various minor edits. Revision D (04/2009) Minor edits. Revision E (05/2010) Updated Table 3-1, Figure 3-1 and Figure 3-2. 2010 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Advance Information DS41342E-page 37 ...
Page 38
... PIC18F1XK50/PIC18LF1XK50 NOTES: DS41342E-page 38 Advance Information 2010 Microchip Technology Inc. ...
Page 39
... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 40
... France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08- Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/05/10 2010 Microchip Technology Inc. ...