PIC18LF13K50T-I/SS Microchip Technology, PIC18LF13K50T-I/SS Datasheet - Page 14

• Manufacturer Part Number: PIC18LF13K50T-I/SS
• Description: 8 KB Flash, 512 RAM, 15 I/O, 10-bit ADC, USB 2.0, NanoWatt XLP 20 SSOP .209in T/
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K50T-I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F1XK50/PIC18LF1XK50
TABLE 4-3:
DS41342E-page 14
Step 1: Direct access to program Flash and enable writes.
Step 2: Point to first row in program Flash.
Step 3: Enable erase and erase single row.
Step 4: Poll WR bit. Repeat until bit is clear.
Step 5: Hold PGC low for time P10.
Step 6: Repeat step 3 with Address Pointer incremented by 64 until all rows are erased.
Step 7: Disable writes.
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0010
0000
4-bit
See Figure 5-4 for details on shift out data timing.
ERASE PROGRAM FLASH CODE SEQUENCE
<MSB><LSB>
Data Payload
8E A6
9C A6
6A F8
6A F7
6A F6
6E F5
84 A6
88 A6
82 A6
50 A6
94 A6
00 00
00 00
00 00
BSF
BCF
BSF
CLRF
CLRF
CLRF
BSF
BSF
NOP
NOP
MOVF EECON1, W, 0
MOVWF TABLAT
NOP
Shift out data
BCF EECON1, WREN
Advance Information
EECON1, FREE
EECON1, WR
Erase starts on the 4th clock of this instruction
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
TBLPTRU
TBLPTRH
TBLPTRL
(1)
Core Instruction
 2010 Microchip Technology Inc.