82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 58
82V2042EPF8
Manufacturer Part Number
82V2042EPF8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V2042EPF8.pdf
(83 pages)
Specifications of 82V2042EPF8
Screening Level
Industrial
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
Table-48 INTS1: Interrupt Status Register 1
4.3.10 COUNTER REGISTERS
Table-49 CNT0: Error Counter L-byte Register 0
Table-50 CNT1: Error Counter H-byte Register 1
PROGRAMMING INFORMATION
IDT82V2042E
DAC_OV_IS
CNT_OV_IS
CNT_H[7:0]
CNT_L[7:0]
TMOV_IS
JAOV_IS
JAUD_IS
Symbol
ERR_IS
Symbol
Symbol
EXZ_IS
CV_IS
(R, Address = 1AH, 3AH)
(R, Address = 1BH, 3BH)
(R, Address = 19H, 39H) (this register is reset and the relevant interrupt request is cleared after a read)
7-0
7-0
Bit
Bit
Bit
6
2
0
7
5
4
3
1
Default
Default
Default
00H
00H
0
0
0
0
0
0
0
0
This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event
= 0: No pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
= 1: The pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event.
= 0: No JA Overflow interrupt event occurred
= 1: JA Overflow interrupt event occurred
This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event.
= 0: No JA Underflow interrupt event occurred
= 1: JA Underflow interrupt event occurred
This bit indicates the occurrence of the interrupt event generated by the detected PRBS/QRSS logic error.
= 0: No PRBS/QRSS logic error interrupt event occurred
= 1: PRBS/QRSS logic error interrupt event occurred
This bit indicates the occurrence of the Excessive Zeros interrupt event.
= 0: No Excessive Zeros interrupt event occurred
= 1: EXZ interrupt event occurred
This bit indicates the occurrence of the Code Violation interrupt event.
= 0: No Code Violation interrupt event occurred
= 1: Code Violation interrupt event occurred
This bit indicates the occurrence of the One-Second Timer Expiration interrupt event.
= 0: No One-Second Timer Expiration interrupt event occurred
= 1: One-Second Timer Expiration interrupt event occurred
This bit indicates the occurrence of the Counter Overflow interrupt event.
= 0: No Counter Overflow interrupt event occurred
= 1: Counter Overflow interrupt event occurred
This register contains the lower eight bits of the 16-bit error counter. CNT_L[0] is the LSB.
This register contains the upper eight bits of the 16-bit error counter. CNT_H[7] is the MSB.
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
58
Description
Description
Description
December 12, 2005
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