IDT77V1253L25PGI IDT, Integrated Device Technology Inc, IDT77V1253L25PGI Datasheet - Page 4

• Manufacturer Part Number: IDT77V1253L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1253L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 3
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
TABLE 1 — SIGNAL DESCRIPTIONS (CONTINUED):
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
RXDATA[15:0]
RXADDR[4:0]
TXADDR[4:0]
TXLED[2:0]
RXPARITY
RXCLAV
TXCLAV
RXREF
RXSOC
TXREF
RXCLK
AGND
AVDD
RXEN
GND
VDD
SE
59, 60, 61, 62, 63, 64,
65, 66, 69, 70, 71, 72,
124, 127, 129, 130,
125, 128, 131, 134,
112, 117, 118, 123,
113, 116, 119, 122,
67, 77, 83, 86, 97,
57, 68, 78, 84, 92,
53, 52, 51, 49, 48
36, 37, 39, 40, 41
2, 11, 44, 50, 56,
1, 5, 16, 38, 45,
PIN NUMBER
PIN NUMBER
PIN NUMBER
73, 74, 75, 76
135, 136, 141
107, 111, 142
13, 14, 15
137, 140
104, 108
102
10
54
46
47
58
55
42
9
16-BIT UTOPIA 2 SIGNALS (MODE[1:0] = 00)
POWER SUPPLY SIGNALS
Out
Out
Out
Out
Out
Out
Out
I/O
I/O
____
____
____
____
I/O
In
In
In
In
In
In
4
Receive Refere nce. Active low, synchronous to OSC. RXREF pulses
low for a programmable number of clock cycles when an x_8 command
byte is received. Re gister 0x40 is programmed to indicate which port
is referenced.
Reserved signal. This input must be connected to logic low.
Ports 2 thru 0 Transmit LED driver. Goes low for 2
cycles, beginning with TXSOC when this port receives a cell for
an X_8 command byte is inserted into the transmit data stream. Logic
portion of the ship, which sources a more constant current than the
digital portion.
portion of the chip, which draws a more constant current than the
digital portion.
Digital Ground.
Digital power supply. 3.3 + 0.3V.
Utopia 2 Receive Address Bus. This bus is used in polling and selecting
Enhanced Control Registers.
Utopia 2 Receive Cell Available. Indicates the cell available status of the
addressed port. It is asserted when a full cell is available for retrieval
RXCLAV is high impedance.
Utopia 2 Receive Clock. This is a free running clock input.
Utopia 2 Receive Data. When one of the three ports is selected, the
Utopia 2 Receive Enable. Driven by an ATM device to indicate its ability
Utopia 2 Receive Data Parity. Odd parity over RXDATA[15:0].
Utopia 2 Receive Start of Cell. Asserted coincident with the first word of
data for each cell on RXDATA.
Utopia 2 Transmit Address Bus. This bus is used in polling and selecting
Enhanced Control Registers.
Utopia 2 Transmit Cell Available. Indicates the availability of room in the
transmission. 8 mA drive current both high and low. One per port.
Transmit Reference. Synchronous to OSC. On the falling edge of TXREF,
for this signal is programmed in register 0x40. Typical application is
WAN timing.
Analog ground. AGND supply a ground reference to the analog
Analog power supply 3.3 + 0.3V AVDD supply power to the analog
the receive port. The port addresses are defined in bits [4:0] of the
from the receive FIFO. When non of the three ports is addressed.
77V1253 transfers received cells to an ATM device across this bus.
Also see RXPARITY.
to receive data across the RXDATA bus.
the transmit port. The port addresses are defined in bits [4:0] of the
transmit FIFO of the addressed port for a full cell. When none of the
three ports is addressed, TXCLAV is high impedance.
SIGNAL DESCRIPTION
SIGNAL DESCRIPTION
SIGNAL DESCRIPTION
23
TCLK or DPICLK
4781tbl 02
IDT77V1253