IDT77V1253L25PGI IDT, Integrated Device Technology Inc, IDT77V1253L25PGI Datasheet - Page 10

• Manufacturer Part Number: IDT77V1253L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1253L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 3
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
77V1253 OVERVIEW:
for 25.6Mbps ATM network communications as defined by ATM Forum
document af-phy-040.000 and ITU-T I.432.5. The physical layer is divided
into a Physical Media Dependent sub layer (PMD) and Transmission Conver-
gence (TC) sub layer. The PMD sub layer includes the functions for the
transmitter, receiver and clock recovery for operation across 100 meters of
category 3 unshielded twisted pair (UTP) cable. This is referred to as the Line
Side Interface. The TC sub layer defines the line coding, scrambling, data
framing and synchronization.
as a switch core or SAR). This cell level interface is configurable as either 8-
bit Utopia Level 1 Multi-PHY, 16-bit Utopia Level 2, or as three 4-bit DPI
interfaces, as determined by two MODE pins. This is referred to as the PHY-
ATM Interface. The pinout and front page block diagram are based on the
Utopia 2 configuration. Table 2 shows the corresponding pin functions for the
other two modes, and Figures 2 and 3 show functional block diagrams.
The 77V1253 is a three-port implementation of the physical layer standard
On the other side, the 77V1253 interfaces to an ATM layer device (such
RxCLAV[2:0]
RxDATA[7:0]
TxDATA[7:0]
TxCLAV[2:0]
RxEN[2:0]
Mode[1:0]
TxEN[2:0]
RxParity
TxParity
RxSOC
AD[7:0]
TxSOC
TxCLK
RxCLK
OSC
ALE
RST
INT
WR
RD
CS
Microprocessor
(Utility Bus)
Multi-PHY
Interface
UTOPIA
Interface
Figure 2. Block Diagram for Utopia Level 1 configuration (MODE[1:0] = 01)
RxREF
TxREF
Tx/Rx ATM
Tx/Rx ATM
Tx/Rx ATM
Cell FIFO
Cell FIFO
Cell FIFO
RxLED[2:0] TxLED[2:0]
Descrambler
Descrambler
Descrambler
Scrambler/
Scrambler/
Scrambler/
3
10
compatibility with it. The 77V1253, however, has additional register features,
and also duplicates most of its registers to provide significant independence
between the three ports.
is an 8-bit muxed address and data bus, controlled by a conventional
asynchronous read/write handshake.
Additional pins permit insertion and extraction of an 8 kHz timing marker, and
provide LED indication of receive and transmit status.
OPERATION AT 51.2 Mbps
also specified to operate at 51.2 Mbps. Except for the doubled bit rate, all other
aspects of operation are identical to the 25.6 Mbps mode. The data rate is
determined by the frequency of the clock applied to the OSC input. OSC is 32
MHz for the 25.6 Mbps line rate, and 64 MHz for the 51.2 Mbps line rate. All
ports operate at the same frequency.
See page 30 for recommended line magnetics. Magnetics for 51.2 Mbps
operation have a higher bandwidth than magnetics optimized for 25.6 Mbps.
The 77V1253 is based on the 77105, and maintains significant register
Access to these status and control registers is through the utility bus. This
In addition to operation at the standard rate of 25.6 Mbps, the 77V1253 is
3
Encoding/
Encoding/
Encoding/
Decoding
Decoding
Decoding
5B/4B
5B/4B
5B/4B
P/S and S/P
P/S and S/P
P/S and S/P
NRZI
NRZI
NRZI
Clock/Data
Clock/Data
Clock/Data
Recovery
Recovery
Recovery
Driver
Driver
Driver
4781 drw 03
+
-
+
-
+
-
+
-
+
-
+
-
IDT77V1253
Tx Port 0
Rx Port 0
Tx Port 1
Rx Port 1
Tx Port 2
Rx Port 2