IDT77V1253L25PGI IDT, Integrated Device Technology Inc, IDT77V1253L25PGI Datasheet - Page 20

• Manufacturer Part Number: IDT77V1253L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1253L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 3
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
UTOPIA LEVEL 1 MULTI-PHY INTERFACE OPTION
Forum document af-phy-0017 and clarified in af-phy-0039. Utopia Level 1 is
essentially the same as Utopia Level 2, but without the addressing, polling and
selection features. Instead of addressing, it utilizes separate TxCLAV, TxEN,
RxCLAV and RxEN signals for each channel of the 77V1254. There are just
one each of the TxSOC and RxSOC signals, which are shared across all three
channels.
also offers the option of a byte mode protocol. Bit 1 of the Master Control
Registers is used to program whether the UTOPIA Level 1 bus is in cell mode
or byte mode. In byte mode, the PHY is allowed to control data transfer on a
byte-by-byte basis via the TXCLAV and RXCLAV signals. In cell mode,
TXCLAV and RXCLAV are ignored once the transfer of a cell has begun. In
every other way the two modes are identical. Cell mode is the default
configuration and is the one described later.
the 77V1253. All Utopia signals are timed to these clocks.
available) to indicate that it has room in its transmit FIFO to accept at least one
53-byte ATM cell. When the ATM layer device is ready to begin passing the
cell, it asserts TXEN (transmit enable) and TXSOC (start of cell), coincident with
the first byte of the cell on TXDATA. TXEN remains asserted for the duration
The UTOPIA Level 1 MULTI-PHY interface operates as defined in ATM
The Utopia 1 signals are summarized below:
TXDATA[7:0]
TXPARITY
TXSOC
TXEN[2:0]
TXCLAV[2:0]
TXCLK
RXDATA[7:0]
RXPARITY
RXSOC
RXEN[2:0]
RXCLAV[2:0]
RXCLK
Transmit and receive both utilize free running clocks, which are inputs to
In the transmit direction, the PHY first asserts TXCLAV (transmit cell
In addition to Utopia Level 2's cell mode transfer protocol, Utopia Level 1
TxCLK
TxCLAV[2:0]
TxEN[2:0]
TxDATA[7:0],
TxPARITY
TxSOC
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
PHY to ATM
ATM to PHY
X
H1
Figure 15. Utopia 1 Transmit Handshake - Single Cell
H2
P44
20
of the cell transfer, but the ATM device may deassert TXEN at any time once the
cell transfer has begun, but data is transferred only when TXEN is asserted.
to receive data. As with transmit, it may be asserted or deasserted at any time.
The PHY asserts RXCLAV to indicate that it has an entire cell to transfer.
for one clock, coincident with the first byte of each cell. Odd parity is utilized across
each 8-bit data field.
and Figures 15 to 21 are examples of the Utopia Level 1 handshake.
In the receive direction, RXEN indicates when the ATM device is prepared
In both transmit and receive, TXSOC and RXSOC (start of cell) is asserted
P45
Figure 14 shows the data sequence for an ATM cell over Utopia Level 1,
Figure 14. Utopia 1 Data Format and Sequence
P46
First
Last
Bit 7
Payload byte 46
Payload byte 47
Payload byte 48
Payload byte 1
Payload byte 2
Payload byte 3
Header byte 1
Header byte 2
Header byte 3
Header byte 4
Header byte 5
P47
Bit 0
4781 drw 15
P48
X
IDT77V1253
4781 drw 16