IDT77V1264L200PGI IDT, Integrated Device Technology Inc, IDT77V1264L200PGI Datasheet - Page 39

• Manufacturer Part Number: IDT77V1264L200PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1264L200PGI

• Number Of Channels: 4
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Enhanced Control 1 Registers
Enhanced Control 2 Registers
RXREF and TXREF Control Register
Addresses: 0x08, 0x18, 0x28, 0x38
7
6
5
4-0
Addresses: 0x09, 0x19, 0x29, 0x39
7-6
5
4
3
2
1
0
Addresses: 0x40
7-6
5
4
3-0
IDT77V1264L200
Bit
Bit
Bit
W
R/W
R/W
R/W
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
0 = not reset
0 = OSC
0 = no swap
Port 0 (Reg 0x08) 00000
Port 1 (Reg 0x18) 00001
Port 2 (Reg 0x28) 00010
Port 3 (Reg 0x38) 00011
0 = RXREF0 (Port 0) RXREF Source Select Selects which of the four ports (0-3) is the source of RXREF.
0000 = not looped
Initial State
Initial State
Initial State
0 = not reset
00
0
0
0
0
0
0
0
Line Rate Control These bits determine the line bit rate relative to the reference clock, as well as the pre-driver
strength for the TXD+/- outputs.
00 Clock multiplier = 1x, pre-driver strength is “standard”
01 Clock multiplier = 2x, pre-driver strength is “standard”
10 Clock multiplier = 4x, pre-driver strength is “strong”
11 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Master Software Reset 1 = Reset. This bit is self-clearing; it isn’t necessary to write “0” to exit reset.
Reserved
RXREF to TXREF Loop Select When set to 0, TXREF is used to generate X_8 timing marker commands.
When set to 1, TXREF input is ignored, and received X_8 timing commands are looped back and added to the transmit
stream of that same port. It is recommended that the RXREF pulse width be set to 2x, 4x, and 8x or greater when the
clock multiplier is set to 1x, 2x, or 4x respectively and bits 3-0 are set to 1. Refer to Figure 7.
Individual Port Software Reset 1= Reset. This bit is self-clearing; It isn’t necessary to write “0” to exit reset. This
bit does not clear the clock multiplier or Utopia Port Address bits.
Transmit Line Clock (or Loop Timing Mode). When set to 0, the OSC input is used as the transmit line clock.
When set to 1, the recovered receive clock is used as the transmit line clock.
VPI/VCI Swap DPI mode only. Receive direction only. See description earlier.
Utopia 2 Port Address When operating in Utopia 2 Mode, these register bits determine the Utopia 2 port address
bit 3: port 3
bit 2: port 2
bit 1: port 1
bit 0: port 0
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Function
Function
Function
December 2004