IDT77V1264L200PGI IDT, Integrated Device Technology Inc, IDT77V1264L200PGI Datasheet - Page 30

• Manufacturer Part Number: IDT77V1264L200PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1264L200PGI

• Number Of Channels: 4
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Counters
(e.g. software drivers) in evaluating communications conditions. It is
anticipated that these counters will be polled from time to time (user
selectable) to evaluate performance. A separate set of registers exists
for each channel of the PHY.
cell count (without roll over) if the counter is read once/second. The
Symbol Error counter and HEC Error counter were given sufficient size
to indicate exact counts for low error-rate conditions. If these counters
overflow, a gross condition is occurring, where additional counter resolu-
tion does not provide additional diagnostic benefit.
to the Counter Select Registers.
Loop Timing Feature
cations where data needs to be repeated / transmitted using the recov-
ered clock. If the loop timing mode is enabled in the Enhanced Control
Register 1 bit 6, the recovered receive clock is used as to clock out data
on transmit side. This mode is port specific, i.e., the user can select one
or more ports to be in loop timing mode. In normal mode, the transmitter
transmits data using the multiplied oscillator clock.
IDT77V1264L200
Several condition counters are provided to assist external systems
The TXCell and RXCell counters are sized (16 bits) to provide a full
Reading Counters
1. Decide which counter value is desired. Write to the Counter
2. Read the Counter Registers (0x04, 0x14, 0x24 or 0x34 (low
Further reads may be accomplished in the same manner by writing
The 77V1264L200 also offers a loop timing feature for specific appli-
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– 8 bits
– counts all invalid 5-bit symbols received
– 16 bits
– counts all transmitted cells
– 16 bits
– counts all received cells, excluding idle cells and HEC errored
– 5 bits
– counts all HEC errors received
Select Register(s) (0x06, 0x16, 0x26 and 0x36) to the bit location
corresponding to the desired counter. This loads the High and
Low Byte Counter Registers with the selected counter’s value,
and resets this counter to zero.
byte)) and (0x05, 0x15, 0x25 or 0x35 (high byte)) to get the value.
Transmit Cell Counters
Receive Cell Counters
Receive HEC Error Counters
Symbol Error Counters
Note: Only one counter may be enabled at any time in each
of the Counter Select Registers.
Note: The PHY takes some time to set up the low and high
byte counters after a specific counter has been selected in the
Counter Selector register. This time delay (in µ S) varies with
the line rate and can be calculated as follows:
cells
Time delay (µ S) =
line rate (Mbps)
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amount of jitter that gets added each time data is transmitted. Table 4
shows the jitter measured at various data rates. The set-up shown in
Figure 35 was used to perform these tests. The maximum jitter seen
was at TX point 5 and the minimum jitter was at point 2. The loop timing
jitter is defined as the amount of jitter generated by each TX node. In
other words, the loop timing jitter or the jitter added by a loop-timed port
in the set-up below is the difference between the Total Output Jitter and
the Total Input Jitter.
Jitter in Loop Timing Mode
One of the primary concerns when using loop timing mode is the
December 2004