IDT77V1264L200PGI IDT, Integrated Device Technology Inc, IDT77V1264L200PGI Datasheet

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Features List ! Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for four 204.8 Mbps ATM channels ! Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5 specifications for 25.6 Mbps physical interface ! Operates at 25.6, ...

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IDT77V1264L200 Applications ! Up to 204.8Mbps backplane transmission ! Rack-to-rack short links ! ATM Switches 77V1264L200 Overview The 77V1264L200 is a four port implementation of the physical layer standard for 25.6Mbps ATM network communications as defined by ATM Forum document ...

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IDT77V1264L200 VDD 1 GND 2 TX0- 3 TX0+ 4 VDD MODE1 7 MODE0 8 RXREF 9 TXREF 10 GND 11 TXLED3 12 TXLED2 13 TXLED1 14 TXLED0 15 VDD 16 TXDATA0 17 TXDATA1 18 TXDATA2 19 TXDATA3 ...

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IDT77V1264L200 Signal Descriptions Signal Name Pin Number RX0+,- 139, 138 RX1+,- 133, 132 RX2+,- 121, 120 RX3+,- 115, 114 TX0+,- 4, 3 TX1+,- 144, 143 TX2+,- 110, 109 TX3+,- 106, 105 Signal Name Pin Number AD[7:0] 101, 100, 99, 98, ...

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IDT77V1264L200 SE 102 TXLED[3:0] 12, 13, 14, 15 TXREF 10 Signal Name Pin Number AGND 112, 117, 118, 123, 124, 127, 129, 130, 135, 136, 141 AVDD 113, 116, 119, 122, 125, 128, 131, 134, 137, 140 GND 2, 11, ...

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IDT77V1264L200 Signal Name Pin Number RXCLAV[3:0] 64, 65, 66, 54 RXCLK 46 RXDATA[7:0] 69, 70, 71, 72, 73, 74, 75, 76 Out RXEN[3:0] 51, 49, 48, 47 RXPARITY 58 RXSOC 55 TXCLAV[3:0] 39, 40, 41, 42 TXCLK 43 TXDATA[7:0] 24, ...

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IDT77V1264L200 Signal Assignment as a Function of PHY/ATM Interface Mode SIGNAL NAME PIN NUMBER VDD 1 GND 2 TX0- 3 TX0+ 4 VDD MODE1 7 MODE0 8 RXREF 9 TXREF 10 GND 11 TXLED3 12 TXLED2 13 ...

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IDT77V1264L200 SIGNAL NAME PIN NUMBER TXADDR3 37 VDD 38 TXADDR2 39 TXADDR1 40 TXADDR0 41 TXCLAV 42 TXCLK 43 GND 44 VDD 45 RXCLK 46 RXEN 47 RXADDR0 48 RXADDR1 49 GND 50 RXADDR2 51 RXADDR3 52 RXADDR4 53 RXCLAV ...

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IDT77V1264L200 SIGNAL NAME PIN NUMBER RXDATA2 74 RXDATA1 75 RXDATA0 76 GND 77 VDD 78 RXLED0 79 RXLED1 80 RXLED2 81 RXLED3 82 GND 83 VDD 84 INT 85 GND 86 RST ALE ...

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IDT77V1264L200 SIGNAL NAME PIN NUMBER GND 111 AGND 112 AVDD 113 RX3- 114 RX3+ 115 AVDD 116 AGND 117 AGND 118 AVDD 119 RX2- 120 RX2+ 121 AVDD 122 AGND 123 AGND 124 AVDD 125 OSC 126 AGND 127 AVDD ...

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IDT77V1264L200 Functional Description Transmission Convergence (TC) Sub Layer Introduction The TC sub layer defines the line coding, scrambling, data framing and synchronization. Under control of a switch interface or Segmenta- tion and Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts ...

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IDT77V1264L200 The output of the 4b/5b encoder provides serial data to the NRZI encoder. The NRZI code transitions the wire voltage each time a '1' bit is sent. This, together with the previous encoding schemes guarantees that long run lengths ...

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IDT77V1264L200 TXCLK TXDATA[7:0] TXParity TXSOC TXEN[3:0] TXCLAV[3:0] UTOPIA Mode[1:0] Multi-PHY Interface RXCLK RXDATA[7:0] RXParity RXSOC RXEN[3:0] RXCLAV[3:0] INT RST AD[7:0] Microprocessor ALE Interface OSC Figure 2 Block Diagram for Utopia Level 1 Configuration (MODE[1:0] = 01) TXRef ...

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IDT77V1264L200 DPICLK Mode[1:0] P0_TCLK P0_TFRM P0_TD[3:0] P0_RCLK P0_RFRM P0_RD[3:0] P1_TCLK P1_TFRM P1_TD[3:0] P1_RCLK P1_RFRM P1_RD[3:0] DPI Multi-PHY Interface P2_TCLK P2_TFRM P2_TD[3:0] P2_RCLK P2_RFRM P2_RD[3:0] P3_TCLK P3_TFRM P3_TD[3:0] P3_RCLK P3_RFRM P3_RD[3:0] INT RST RD Microprocessor WR Interface CS AD[7:0] ALE OSC ...

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IDT77V1264L200 PHY-ATM Interface The 77V1264L200 PHY offers three choices in interfacing to ATM layer devices such as segmentation and reassembly (SAR) and switching chips. MODE[1:0] are used to select the configuration of this interface, as shown in the table below. ...

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IDT77V1264L200 NRZI RX + Decoding RX Synthesizer UTOPIA Level 1 Multi-phy Interface Option The UTOPIA Level 1 MULTI-PHY interface is based on ATM Forum document af-phy-0017. Utopia Level 1 is essentially the same as Utopia Level 2, but without the ...

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IDT77V1264L200 RXRef#0 (X_8 received) RXRef#1 (X_8 received) RXRef#2 (X_8 received) RXRef#3 (X_8 received) RXRefSel[1:0] The Utopia 1 signals are summarized below: TXRef Input LTSel#0 Mux LTSel#1 Mux LTSel#2 Mux LTSel#3 Mux RXRef Select IDT77V1264L200 Decoder IDT77V1254 RXRef Output Figure 7 ...

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IDT77V1264L200 Transmit and receive both utilize free running clocks, which are inputs to the 77V1264L200. All Utopia signals are timed to these clocks. In the transmit direction, the PHY first asserts TXCLAV (transmit cell available) to indicate that it has ...

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IDT77V1264L200 polling: TXCLK TXADDR[4:0] 1F TXCLAV N+1 TXEN TXData[15:0], P39, 40 P41, 42 TXPARITY TXSOC cell transmission to: polling: TXCLK TXADDR[4:0] 1F TXCLAV N+1 TXEN TXData[15:0], P43, 44 P45, 46 TXPARITY TXSOC PHY N cell transmission to: selection polling N+3 ...

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IDT77V1264L200 polling: TXCLK TXADDR[4:0] 1F TXCLAV N+1 TXEN TXData[15:0], P25, 26 TXPARITY TXSOC PHY M cell transmission to: Figure 11 Utopia 2 Transmit Handshake - Transmission Suspended polling: RXCLK RXADDR[4:0] N+3 RXCLAV RXEN RXData[15:0], P39, 40 P41, 42 RXPARITY RXSOC ...

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IDT77V1264L200 polling: RXCLK RXADDR[4:0] N+3 RXCLAV RXEN RXData[15:0], P45, 46 P47, 48 RXPARITY RXSOC PHY N+3 cell transmission to: polling polling: RXCLK RXADDR[4:0] N+3 RXCLAV RXEN RXData[15:0], P25, 26 RXPARITY RXSOC PHY M cell transmission from: Figure 14 Utopia 2 ...

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IDT77V1264L200 TXCLK TXCLAV[3:0] TXEN[3:0] TXDATA[7:0], P46 TXPARITY TXSOC Figure 16 Utopia 1 Transmit Handshake - Back-to-Back Cells, and TXEN Suspended Transmission TXCLK TXCLAV[3:0] TXEN[3:0] TXDATA[7:0], P42 P43 TXPARITY TXSOC Figure 17 Utopia 1 Transmit Handshake - TXEN Suspended Transmission and ...

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IDT77V1264L200 RXCLK RXCLAV[3:0] RXEN[3:0] RXDATA[7:0], P47 P48 RXPARITY RXSOC Figure 19 Utopia 1 Receive Handshake - RXEN and RXCLAV Control RXCLK RXCLAV[3:0] RXEN[3:0] High-Z RXDATA[7:0], P42 RXPARITY High-Z RXSOC RXCLK RXCLAV[3:0] RXEN[3:0] High-Z RXDATA[7:0], RXPARITY High-Z RXSOC Figure 21 Utopia ...

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IDT77V1264L200 DPI Interface Option The DPI interface is relatively new and worth additional description. The biggest difference between the DPI configurations and the UTOPIA configurations is that each channel has its own DPI interface. Each interface has a 4-bit data ...

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IDT77V1264L200 P_RCLK (in) P_RFRM (out) P_RD(3: (out) P_RCLK (in) P_RFRM (out) P_RD(3: (out) P_RCLK (in) P_RFRM (out) Cell 1 Cell 1 P_RD(3:0) (out) Nibble 104 Nibble 105 Figure 25 DPI Receive Handshake - ATM Layer Device ...

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IDT77V1264L200 P_TCLK (out) P_TFRM (in) P_TD(3: (in) Figure 27 DPI Transmit Handshake - One Cell for Transmission P_TCLK (out) P_TFRM (in) P_TD(3: (in) Figure 28 DPI Transmit Handshake - Back-to-Back Cells for Transmission P_TCLK (out) P_TFRM ...

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IDT77V1264L200 Control and Status Interface Utility Bus The Utility Bus is a byte-wide interface that provides access to the registers within the IDT77V1264L200. These registers are used to select desired operating characteristics and functions, and to communicate status to external ...

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IDT77V1264L200 P_TCLK (out) P_TFRM (in) Cell 1 Cell 1 P_TD(3:0) (in) Nibble 104 Nibble 105 Diagnostic Functions Loopback There are two loopback modes supported by the 77V1264L200. The loopback mode is controlled via bits 1 and 0 of the Diagnostic ...

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IDT77V1264L200 ATM Layer Device ATM Layer Device ATM Layer Device IDT77V1254 TC sublayer PMD sublayer Figure 32 Normal Mode IDT77V1254 PMD sublayer TC sublayer Figure 33 PHY Loopback IDT77V1254 TC sublayer sublayer Figure 34 Line Loopback IDT77V1264L200 ...

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IDT77V1264L200 Counters Several condition counters are provided to assist external systems (e.g. software drivers) in evaluating communications conditions anticipated that these counters will be polled from time to time (user selectable) to evaluate performance. A separate set of ...

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IDT77V1264L200 OSC Normal Mode Loop Timing Jitter Specification Line Rate Data Rate Mbps 32 64 128 256 The waveforms below show some of the measurements taken with the set-up in Figure 35. Using the formula above, ...

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IDT77V1264L200 Jitter at 25.6Mbps at point 4 with respect to point 1 Jitter at 51.2Mbps at point 4 with respect to point 1 Jitter at 25.6Mbps at point 5 with respect to point 1 Jitter at 51.2Mbps at point 5 ...

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IDT77V1264L200 Jitter at 102.4Mbps at point 4 with respect to point 1 Jitter at 256Mbps at point 4 with respect to point 1 From the above measurements taken, the amount of jitter being added at each TX point is not ...

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IDT77V1264L200 Line Side (Serial) Interface Each of the four ports has two pins for differential serial transmission, and two pins for differential serial receiving. PHY to Magnetics Interface A standard connection to 100 and 120 unshielded twisted pair cabling is ...

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IDT77V1264L200 Status and Control Register List The 77V1264L200 has 41 registers that are accessible through the utility bus. Each of the four ports has 9 registers dedicated to that port. There is only one register (0x40) which is not port ...

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IDT77V1264L200 Master Control Registers Addresses: 0x00, 0x10, 0x20, 0x30 Bit Type Initial State discard errored cells Discard Receive Error Cells - On receipt of any cell with an error (e.g. short cell, invalid ...

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IDT77V1264L200 Addresses: 0x02, 0x12, 0x22, 0x32 Bit Type Initial State 6 R UTOPIA 5 R tri-state 4 R normal 3 R normal 2 R normal 1,0 R normal ...

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IDT77V1264L200 Low Byte Counter Registers [7:0] Addresses: 0x04, 0x14, 0x24, 0x34 Bit Type Initial State [7:0] R 0x00 High Byte Counter Registers [15:8] Addresses: 0x05, 0x15, 0x25, 0x35 Bit Type Initial State [7:0] R 0x00 Counter Select Registers Addresses: 0x06, ...

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IDT77V1264L200 Enhanced Control 1 Registers Addresses: 0x08, 0x18, 0x28, 0x38 Bit Type Initial State not reset 6 R OSC 5 R swap 4-0 R/W Port 0 (Reg 0x08) 00000 Port 1 ...

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IDT77V1264L200 Absolute Maximum Ratings Symbol VTERM TBIAS TSTG IOUT Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these ...

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IDT77V1264L200 DC Electrical Characteristics (TX+/- Output Pins Only) Symbol V Output Logic High Voltage OH1 V Output Logic Low Voltage OL DC Electrical Characteristics (RXD+/- Input Pins Only) Symbol V RXD+/- input voltage range IR V RXD+/- input peak-to-peak differential ...

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IDT77V1264L200 t 3 TXCLK TXDATA[15:0], Octet 1 TXPARITY t 5 TXADDR[4: TXSOC TXEN High-Z TXCLAV RXCLK t 14 RXEN t 16 RXADDR[4:0] High-Z RXCLAV High-Z RXSOC RXDATA[15:0], High-Z RXPARITY t 4 Octet ...

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IDT77V1264L200 UTOPIA Level 1 Bus Timing Parameters Symbol t31 TXCLK Frequency t32 TXCLK Duty Cycle (% of t31) t33 TXDATA[7:0], TXPARITY Setup Time to TXCLK t34 TXDATA[7:0], TXPARITY Hold Time to TXCLK t35 TXSOC, TXEN[3:0] Setup Time to TXCLK t36 ...

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IDT77V1264L200 DPI Bus Timing Parameters Symbol t51 DPICLK Frequency t52 DPICLK Duty Cycle (% of t51) t53 DPICLK to Pn_TCLK Propagation Delay t54 Pn_TFRM Setup Time to Pn_TCLK t55 Pn_TFRM Hold Time to Pn_TCLK t56 Pn_TD[3:0] Setup Time to Pn_TCLK ...

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IDT77V1264L200 Utility Bus Read Cycle Name Tas Tcsrd Tah Tapw Ttria Trdpw Tdh Tch Ttrid Trd Tar Trdd Utility Bus Write Cycle Name Tapw Tas Tah Tcswr Twrpw Tdws Tdwh Tch Taw AD[7:0] (input) ALE CS RD AD[7:0] (output) Min. ...

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IDT77V1264L200 AD[7:0] ALE CS WR OSC, RXREF, TXREF and Reset Timing Symbol Tcyc OSC cycle period Tch OSC high tim Tcl OSC low time Tcc OSC cycle to cycle period variation 1 Trrpd OSC to RXREF Propagation Delay Ttrh TXREF ...

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IDT77V1264L200 AC Test Conditions A note about Figures 47 and 48: The ATM Forum and ITU-T standards for 25 Mbps ATM define "Network" and "User" interfaces. They are identical except that transmit and receive are switched between the two. A ...

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IDT77V1264L200 Note 1 AGND RJ45 Magnetics Connector RJ45 Magnetics RJ45 Magnetics RJ45 Magnetics Note: 1.No power or ground plane inside this area. ...

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IDT77V1264L200 Ordering Information IDT NNNNN A Device Type Power Revision History September 20, 2001: Initial publication. December 6, 2001: Added DPI information. December 9, 2004: Removed Commerical Temperature Range throughout datasheet, updated IDT logo and datasheet to current template. CORPORATE ...