IDT77V1264L200PGI IDT, Integrated Device Technology Inc, IDT77V1264L200PGI Datasheet - Page 18

• Manufacturer Part Number: IDT77V1264L200PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1264L200PGI

• Number Of Channels: 4
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

one 53-byte ATM cell. When the ATM layer device is ready to begin passing the cell, it asserts TXEN (transmit enable) and TXSOC (start of cell), coin-
cident with the first byte of the cell on TXDATA. TXEN remains asserted for the duration of the cell transfer, but the ATM device may deassert TXEN at
any time once the cell transfer has begun, but data is transferred only when TXEN is asserted.
any time. Note, however, that not more than one RXEN should be asserted at a time. Also, once a given RX port is selected, that port's FIFO must be
emptied of cells (as indicated by RXCLAV) before a different RX port may be enabled.
utilized across each 8-bit data field.
IDT77V1264L200
Transmit and receive both utilize free running clocks, which are inputs to the 77V1264L200. All Utopia signals are timed to these clocks.
In the transmit direction, the PHY first asserts TXCLAV (transmit cell available) to indicate that it has room in its transmit FIFO to accept at least
In the receive direction, RXEN indicates when the ATM device is prepared to receive data. As with transmit, it may be asserted or deasserted at
In both transmit and receive, TXSOC and RXSOC (start of cell) is asserted for one clock, coincident with the first byte of each cell. Odd parity is
Figure 8 shows the data sequence for an ATM cell over Utopia Level 1, and Figures 15 through 21 are examples of the Utopia Level 1 handshake.
Figure 8 Utopia 1 Data Format and Sequence
Last
First
Bit 7
Payload byte 46
Payload byte 47
Payload byte 48
Payload byte 1
Payload byte 2
Payload byte 3
Header byte 1
Header byte 2
Header byte 3
Header byte 4
Header byte 5
18 of 49
Bit 0
3505 drw 15
.
December 2004