MSC8144ADS Freescale, MSC8144ADS Datasheet - Page 45

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MSC8144ADS

Manufacturer Part Number
MSC8144ADS
Description
Manufacturer
Freescale
Datasheet

Specifications of MSC8144ADS

Lead Free Status / RoHS Status
Compliant
5.12.3.3
The BCSR implemented on the MSC8144 is the Altera EPM1270F256-5. The FPGA resides on
LBIU in the CS1 Memory Space. The Register File may achieve 32 8-bit slices. CS1 configures
as GPCM. Figure 5-17 shows the signal connections between the FPGA and the MPC8560
Multiplexed Local bus.
Freescale Semiconductor
BCSR on FPGA (optional)
Figure 5-15. DS3 Framer on LBIU Timings
MPC8560
LAD[16–31]
LBIU
LAD[0–7]
LGPL2
LWE0
Figure 5-16. DS3 on the LBIU
CS2
ALE
MSC8144ADS MSC8144, Rev. 0
from FPGA
nDS3RST
PTYPE[0–2] = 000
for Intel Asynchronous
CS
ALE/AS
A[14–0]
D[7–0]
RD/DS/
WR/R/W
RESET
mode
XRT79L71
Reset Operation and Configuration
5-21