MSC8144ADS Freescale, MSC8144ADS Datasheet - Page 37

• Manufacturer Part Number: MSC8144ADS
• Manufacturer: Freescale

Specifications of MSC8144ADS

• Lead Free Status / RoHS Status: Compliant

5.9.3 Hard Reset Configuration
There are two reset systems on the board:
The JTAG debug access for the processors is independent: via the COP connector for the
MPC8560, and via the OnCE connector for the MSC8144. There are two reset signals: (nHRSTh
and nHRST), and these initiate the appropriate processor and its peripherals separately. The user
can configure the Board so that the JTAG interface is connected in a chain. This means that
debug access to both processors is available from the OnCE header and a debugger will initiate
all board devices with a single reset signal (in this case, the two reset signals nHRSTh and
nHRST have a logical connection in the FPGA). In additional any MPC8560 internal reset will
reset the MSC8144 as well.
Table 5-6 and Table 5-7 show the Reset Configuration Word settings for normal ethernet and
reduced mode Ethernet (RMII, SMII) configurations.
Freescale Semiconductor
31–29
28–23
22
21-20
Bits
„ Host processor (MPC8560) reset
„ MSC8144 reset
-
PTE
-
RS_RCS
Name
Switch
DIP
nPRST
Reserved
RapidIO Prescale
Timer Enable
Reserved
RapidIO/SGMII
Reference Clock
Select
Meaning
Figure 5-9. Configuration Scheme
MSC8144ADS MSC8144, Rev. 0
Table 5-6. RCW Low
Reserved
RIO prescaler timer
enabled.OCeaN clock
is 200 MHz
Reserved
RCW3. Selects
whether to enable or
disable power to the
RapidIO and Ethernet
blocks.
Normal Mode from Boot EEPROM
Reg. Array
FPGA
Setting
nSRST
000
011000
0
-
Value
Reset Operation and Configuration
MSC8144
Reserved
RIO prescaler timer
enabled.OCeaN clock
is 200 MHz
Reserved
RIO/SGMII reference
Clock is 100MHz.
RS[0-2] within ‘011’ to ‘111
Setting
Reduced Mode
000
011000
0
00
Value
5-13