MSC8144ADS Freescale, MSC8144ADS Datasheet - Page 44

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MSC8144ADS

Manufacturer Part Number
MSC8144ADS
Description
Manufacturer
Freescale
Datasheet

Specifications of MSC8144ADS

Lead Free Status / RoHS Status
Compliant
ADS Functional Description
5.12.3.2
The DS3/E3 framer is the Intel XRT79L71. It is located on the CS2 Memory Controller and is set
by three PTYPE[0:2] pins. This device requires LBIU GPCM programming. The XRT79L71
resets via the host HRST_REQ output signal or by setting BCSR2[0] = 0. Figure 5-15 shows the
read/write timing for the DS3 framer. Figure 5-16 shows the signal connections between the DS3
framer and the MPC8560 Multiplexed Local bus.
5-20
DS3 Framer on LBIU
Figure 5-14. Flash memory to Host Signal Connections
Figure 5-13. Flash Memory Synchronous Read Timing
MPC8560
LAD[0–15]
LAD[8–26]
LA[27–30]
LBIU
LGPL2
LAD[7]
LWE0
CLK
CS0
ALE
MSC8144ADS MSC8144, Rev. 0
nPRST
<40MHz
CLK
CE#
ADV#
DQ[15–0]
A[23–5]
(A[24]) 32MB
A[4–1]
OE#
WE#
RST#
StrataFlash
P30
Freescale Semiconductor