MSC8144ADS Freescale, MSC8144ADS Datasheet - Page 36

• Manufacturer Part Number: MSC8144ADS
• Manufacturer: Freescale

Specifications of MSC8144ADS

• Lead Free Status / RoHS Status: Compliant

ADS Functional Description
5.9.1 Reset Connectivity
Figure 5-8 shows the reset connectivity scheme. Section 5.9.2 and Section 5.9.3 describe the reset
procedures.
5.9.2 PORESET Configuration
When PORESET is deasserted, six signals are sampled: DDR_VSEL, GE1_VSEL, GE2_VSEL,
CLKINRNG, LDFAIL, and SOURCE[0–2]. The CFG_RCW [0–16] or HCW for Reduced
Configuration Mode is also sampled during the assertion of PORESET. Default settings are listed
below:
When the reset configuration is loaded from I
which indicates boot error.
These initiate values are defined by DIP-switch values latched into the FPGA BCSRs during
PORESET and driven towards the appropriate MSC8144 pins until SRESET is deasserted. The
RCW[0–16] configuration signals used for Reduced Configuration Word apply the similar way.
5-12
„ SOURCE[0–2] = 011 meaning Reduced Configuration Mode.
„ DDR_VSEL = 0 to support DDR2.
„ GE1_VSEL and GE2_VSEL are both 1 for GETH 2.5 V operation for RGMII mode.
„ CLKINRNG = 0 for CLKIN 66 MHz.
“SIG0”
“SIG1”
From COP
From OnCE
“RDY”
SRST
“PG”
HRST
pin 13
pin 9
HRST
PRST
SRST
NMI
Note: PD means Pull-Down, PU means Pull-Up
nHRSTc
nHRSTo
Figure 5-8. ADS Reset Scheme
FPGA
nHRST_REQ
MSC8144ADS MSC8144, Rev. 0
nREADY
nHRSTh
nSRSTh
nHRST
nPRST
nSRST
2
C EEPROM, the LDFAIL output becomes high
From PS
PG
PU
PU
PU
PD
HRESET
SRESET
READY
PORESET
HRESET
SRESET
MPC8560
MSC8144
HRESET_REQ
Freescale Semiconductor