MSC8144ADS Freescale, MSC8144ADS Datasheet - Page 42

• Manufacturer Part Number: MSC8144ADS
• Manufacturer: Freescale

Specifications of MSC8144ADS

• Lead Free Status / RoHS Status: Compliant

ADS Functional Description
It is possible to configure the ADS so that all peripherals are programmed from MSC8144. If
configured this way, the MPC8560 must be set in reset state in order to avoid contention on the
parallel control bus (do: SW2[1] = 1).
5.12.1
After the reset procedure is completed, the host has the following default clock values:
Table 5-8 shows reset signals for the Host, their default values, and a description for each signal.
5-18
TSEC1_TXD[6:4]
TSEC2_TXD[6:5]
TSEC2_TXD[2:4]
„ CPM FCC2 MII/RMII port;
„ Eight CPM MCC TDM ports;
„ Two I2C bus controllers: dedicated and CPM based;
„ Dedicated UART.
„ CPU clock 667 MHz,
„ CPM and CCB 266 MHz,
„ DDR 133 MHz (266 MHz Data Rate),
„ LBC 32 MHz with SYSCLK 66 MHz
TSEC1_TXD7,
TSEC2_TXD7
nPCI_REQ64
Signal Name
LALE,LGPL2
nPCI_GNT4
nPCI_GNT3
nPCI_GNT2
nPCI_GNT1
EC_MDC
LA[28:31]
LA27
Host Configuration
The PCI interface operates as a 32-bit interface
42Ohm/25Ohm I/O drivers are used on the PCI
The e500 core is allowed to boot without waiting
One added buffer delay (default) (zero added
Ethernet interfaces operate in reduced mode
The on-chip PCI arbiter is enabled/disable
Table 5-8. MPC8560 Reset Configuration Signals
for configuration by an external master
Boot ROM is on local bus 16-bit Flash
PCI operates in normal mode
buffer delays for LALE)
PCI Mode. Non PCI-X
cfg_pll_core[0:1]
cfg_sys_pll[0:3]
RGMII mode
RapidIO ID
interface
Mode
MSC8144ADS MSC8144, Rev. 0
CCB/SYSCLK = 4
Core/CCB = 3
Value
0100
110
1/0
1/0
0,0
11
11
10
1
1
1
0
1
Freescale Semiconductor
4.7k Pull-Up/Down
4.7k Pull-Up/Down
Internal Pull-Up
Internal Pull-Up
Internal Pull-Up
Internal Pull-Up
Internal Pull-Up
4.7k Pull-Down
4.7k Pull-Down
4.7k Pull-Down
4.7k Pull-Up or
4.7k Pull-Up or
Implemented
4.7k Pull-Up
Pull-Down
Pull-Down
Pull-Up