DLP-HS-FPGA2 DLP Design Inc, DLP-HS-FPGA2 Datasheet - Page 12
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DLP-HS-FPGA2
Manufacturer Part Number
DLP-HS-FPGA2
Description
Interface Modules & Development Tools USB FPGA Module w/ Xilinx XC3S400A
Manufacturer
DLP Design Inc
Series
-r
Datasheet
1.DLP-HS-FPGA2.pdf
(21 pages)
Specifications of DLP-HS-FPGA2
Interface Type
USB
Description/function
USB - FPGA Module
Dimensions
71.1 mm x 30.5 mm x 5.3 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Number Of Channels
2
Operating Supply Voltage
3.6 V to 6 V
Product
Interface Modules
Supply Voltage (max)
6 V
Supply Voltage (min)
3.6 V
Wireless Frequency
66 MHz
Main Purpose
Interface, USB to FPGA
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
FT2232D, XC3S400A-4FTG256C
Primary Attributes
-
Secondary Attributes
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
Xilinx Spartan 3A, FTDI FT2232H Dual-Channel High-Speed USB IC
The USER I/O Pin Read/Set/Clear Commands I/O number mapping to the physical I/O pins on the
DLP-HS-FPGA board are described in the following table:
Rev. 1.3 (March 2011)
I/O Number
Memory
0x0C (12)
0x0D (13)
0x0A (10)
0x0B (11)
0x00 (0)
0x01 (1)
0x02 (2)
0x03 (3)
0x04 (4)
0x05 (5)
0x06 (6)
0x07 (7)
0x08 (8)
0x09 (9)
Write
Writes 4
bytes to the
DDR
SDRAM
FPGA Pin
J1 Pin 10
J1 Pin 12
J1 Pin 13
J1 Pin 14
J1 Pin 15
J1 Pin 16
DLP-HS-
J1 Pin 2
J1 Pin 3
J1 Pin 4
J1 Pin 5
J1 Pin 6
J1 Pin 7
J1 Pin 8
J1 Pin 9
XC3S200A
XC3S400A
0
1
2
3
4
5
6
7
D13
C13
D11
C12
C10
A14
A13
C11
A11
Pin
D9
C8
D8
A6
B6
0xam
0x9n
0xah
0xd0
0xd1
0xd2
0xd3
0xal
XC3S200A
XC3S400A
Writes 4 bytes to the DDR2 SDRAM starting with the
address specified. The command byte is OR’d with the
Most Significant Row Address bit (24).
Bits 23-16 Middle 8 bits of Row Address to be written to
Bits 15-12 Lower 4 bits of Row Address to be written to
Bits 11-8 Upper 4 bits Column Address to be written to
Bits 7-2: Lower 6 bits of column address to be written to
NOTE: Refer to the text above regarding Column Bits 1
and 0 (equates to 0xal bits 3-2). Bits 1-0: Bank Address
to be written to
Data Byte 0 written to Address Specified
Data Byte 1 written to Address Specified + 1
Data Byte 2 written to Address Specified + 2
Data Byte 3 written to Address Specified + 3. Returns
the 4 bytes written followed by an echo back of the
command and address data sent.
NOTE: If the memory has not been initialized, the
command returned will be 0xE7 indicating the error.
TABLE 2
User I/O
Bank
n = 0 the Most Sig Row Address bit is low (0x90)
n = 1 the most Sig Row Address bit is high (0x91)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12
FPGA Pin Configurations Available
Digital Input, Output, Differential Pair 0+
Digital Input, Output, Differential Pair 0-
Digital Input, Output, Differential Pair 1-
Digital Input, Output, Differential Pair 1+
Digital Input, Output, Differential Pair 2+,
Global Clock
Digital Input, Output, Differential Pair 2-,
Global Clock
Digital Input, Output, Differential Pair 3+,
Global Clock
Digital Input, Output, Differential Pair 3-,
Global Clock
Digital Input, Output, Differential Pair 4+
Digital Input, Output, Differential Pair 4-
Digital Input, Output, Differential Pair 5+
Digital Input, Output, Differential Pair 5-
Digital Input, Output, Differential Pair 6+
Digital Input, Output, Differential Pair 6-
© DLP Design, Inc.