STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 71

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VII - EXTERNAL REGISTERS
These registers are located in shared memory. Initiate Block Address Registers (IBAR1 and IBAR2) give
respectively the Initiate Block Address (IBA1 and IBA2) in shared memory.
From IBA1 the different addresses are obtained:
• Initialization Block address concerning the first HDLC Controller (HDLC1)
• HDLC interrupt Queue for the first HDLC Controller (HDLC1) and the second (HDLC2)
• MON interrupt Queue
• C/I interrupt Queue
From IBA1 only the following address is obtained:
• Initialization Block address concerning the second HDLC Controller (HDLC2)
‘Not used’ bits (Nu) are accessible by the microprocessor but the use of these bits by software is not rec-
ommended.
VII.1 - Initialization Block in External Memory (IBA1 and IBA2)
When Direct Memory Access Controller receives START from one of 64 channels, it reads initialization
block immediately to know the first address of the first descriptor for this channel.
Bit 0 of Transmit Descriptor Address (TDA Low) and bit 0 of Receive Descriptor Address (RDA Low), are
at ZERO mandatory. This Least Significant Bit is not used by DMA Controller, the shared memory is al-
ways a 16 bit memory for the DMA Controller.
The Receive Descriptor Address (RDA) is never modified by the RX DMA Controller in this Initialization
Block
N.B. If several descriptors are used to transmit the current frame then before transmitting frame, TX DMA
Controller stores the address of the first Transmit Descriptor Address (TDA) into this Initialization Block if
BOF bit is at “1” (See Transmit Descriptor).
CH 31
CH30
CH 0
CH 2
CH1
to
Channel
R
R
R
T
T
T
Address
IBA+246
IBA+248
IBA+250
IBA+252
IBA+254
IBA+00
IBA+02
IBA+04
IBA+06
IBA+08
IBA+10
IBA+12
IBA+14
IBA+16
to
bit15
Descriptor Address
Not used
Not used
Not used
Not used
Not used
Not used
Transmit Descriptor Address (TDA Low)
Transmit Descriptor Address (TDA Low)
Transmit Descriptor Address (TDA Low)
Receive Descriptor Address (RDA Low)
Receive Descriptor Address (RDA Low)
Receive Descriptor Address (RDA Low)
bit8
bit7
RDA High
RDA High
RDA High
TDA High
TDA High
TDA High
STLC5466
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bit0