STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 45

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VI.10 - Sequence Fault Counter Register
When this register is read by the microprocessor, this register is reset (0000)H.
F0/15
• NB. As the SFCR is reset after reading, a 8-bit microprocessor must read the LSB that will represent the
VI.11 - Time Slot Assigner Address Register 1
READ
TS0/4
HDI
• N.B. After software reset (bit 2 of IDCR Register) or pin reset the automate above mentioned is working.
VI.12 - Time Slot Assigner Data Register 1
CH0/4
V1/8
bit15
bit15
bit15
F15
TS4
V11
number of faults between 0 and 255. To avoid overflow escape notice, it is necessary to start counting
at FF00h, by writing this value in SFCR before launching PRSA. If there are more than FFh errors,
the SFCO interrupt bit (see interrupt register IR -38H address) will signal that the fault count register
has reached the value FFFFh (because of the number of faults exeeded 255).
The automate is stopped when the microprocessor writes TAAR Register with HDI = 0.
F14
TS3
V10
: FAULT0/15
: READ MEMORY
: TIME SLOTS0/4
: HDLC1 INIT
: CHANNEL0/4
: VALIDATION
Number of faults detected by the Pseudo Random Sequence analyser if the analyser has been
validated and has recovered the receive sequence.
When the Fault Counter Register reaches (FFFF)H it stays at its maximum value.
READ = 1, Read Time slot Assigner Memory 1.
READ = 0, Write Time slot Assigner Memory 1.
These five bits define one of 32 time slots in which a channel is set-up or not.
HDI = 1, TSA1 Memory, Tx HDLC1, Tx DMA1, Rx HDLC1, Rx DMA1 and GCI controllers are
reset within 250 microseconds at the most. An automate writes data from Time slot Assigner
Data Register1 (TADR1) (except CH0/4 bits) into each TSA Memory location. If the microproc-
essor reads Time slot Assigner Memory 1 after HDLC INIT, CH0/4 bits of Time slot Assigner
Data Register are identical to TS0/4 bits of Time slot Assigner Address Register 1.
HDI = 0, Normal state.
These five bits define one of 32 channels associated to time slot defined by the previous Register
1(TAAR1).
The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit at 1 re-
spectively.
V1 to V8 are at “0’: the subchannels are ignored.
V1 corresponds to the first bit received during the current time slot.
V1 at 1: the first bit of the current time slot is taken into account in reception and in transmission the
first bit transmitted is taken into account.
V8 at 1: the last bit of the current time slot is taken into account in reception the last bit received and
in transmission the last bit transmitted in transmission.
F13
TS2
V9
TS1
F12
V8
TS0 READ
F11
V7
F10
V6
Nu
V5
F9
After reset (0000)
After reset (0100)
After reset (0000)
HDI
bit8
bit8
bit8
F8
V4
bit7
bit7
bit7
F7
V3
r
H
H
H
F6
V2
e
F5
V1
s
CH4
F4
e
CH3
F3
r
CH2
F2
v
TAAR1 (14)
TADR1 (16)
STLC5466
SFCR (12)
CH1
F1
e
45/130
CH0
bit0
bit0
bit0
F0
d
H
H
H