STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 50

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
VI.15 - Address Field Recognition Address Register 1
The write operation is launched when AFRAR is written by the microprocessor.
AMM : Access to Mask Memory
READ : READ ADDRESS FIELD RECOGNITION MEMORY
CH0/4 : These five bits define one of 32 channels in reception
VI.16 - Address Field Recognition Data Register 1
AF0/15 : ADDRESS FIELD BITS
50/130
bit15
AFM0/
15
AR21
CH4
AFM15
Second Byte
AF15/
bit15
1
1
1
1
1
1
CH3
AFM14
AR20
AF14/
AMM=1, Access to Address Field Recognition Mask Memory.
AMM=0, Access to Address Field Recognition Memory.
READ=1, READ AFR MEMORY.
READ=0, WRITE AFR MEMORY.
: ADDRESS FIELD BIT MASK0/15 if AMM=1 (AMM bit of AFRAR1)
0
0
1
1
1
1
AF0/7; First byte received; AF8/15: Second byte received.
These two bytes are stored into Address Field Recognition Memory when AFRAR1 is written
by the microprocessor.
AMF0/7. When AR10=1 (See HRCR1) each bit of the first received byte is compared respectively to AFx
bit if AFMx=0. In case of mismatching, the received frame is ignored. If AFMx=1, no comparison between
AFx and the corresponding received bit.
AMF8/15. When AR20=1 (See HRCR1) each bit of the second received byte is compared respectively to
AFy bit if AFMy=0. In case of mismatching, the received frame is ignored. If AFMy=1, no comparison be-
tween AFy and the corresponding received bit.
These two bytes are stored into Address Field Recognition Mask Memory when AFRAR 1 is written by
the microprocessor (AMM=1).
CH2
AFM13
AF13/
AR11
First Byte
1
1
0
0
1
1
CH1
AFM12
AF12/
AR10
0
1
0
1
0
1
CHO READ AMM
AFM11
AF11/
The value of the first received byte must be equal to all “1”s and the value of the
second received byte must be equal to “1” also.
The value of the first received byte must be equal either to that of AF0/7 or to “1”
and the value of the second received byte must be equal to all “1”s.
The value of the second received byte must be equal either to that of AF8/15 or
to all “1”s.
The value of the first received byte must be equal to that of AF0/7 bits and the
value of the second received byte must be equal either to that of AF8/15 or to all
“1”s.
The value of the first received byte must be equal to “1” and the value of the sec-
ond received byte must be equal either to that of AF8/15 or to all “1”s.
The value of the first received byte must be equal either to that of AF0/7 or to “1”
and the value of the second received byte must be equal either to that of AF8/15
or to all “1”s.
AFM10
AF10/
AFM9
After reset (0000)
After reset (0000)
AF9/
bit8
Nu
AFM8
AF8/
bit8
Conditions to Receive a Frame
bit7
r
AFM7
AF7/
bit7
H
H
e
AFM6
AF6/
AFM5
s
AF5/
AFM4
AF4/
e
AFM3
AF3/
r
AFM2
AF2/
v
AFRAR1 (1C)
AFRDR1 (1E)
AFM1
AF1/
e
AFM0
AF0/
bit0
bit0
d
H
H