STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 15

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

III.1.4 - Loop Back Function
Any time slot of an Output TDM can be internally
looped back on the time slot which has the same
TDM number and the same TS number
In the case of a bidirectional connection, only the
one specified by the microprocessor is concerned
by the loop back (see Figure).
III.1.5 - Delay through the Matrix
III.1.5.1 - Variable Delay Mode
In the variable delay mode, the delay through the
matrix depends on the relative positions of the in-
put and output time slots in the frame.
So, some limits are fixed:
– the maximum delay is a frame + 2 time slots,
– the minimum delay is programmable.
All the possibilities can be ranked in three cases:
a) If OTSy > ITSx + n then the variable delay is:
b) If ITSx < OTSy < ITSx+n then the variable delay
is:
c) OTSy < ITSx then the variable delay is:
N.B. Rule b) and rule c) are identical.
For n = 1 and n = 2, (see Figure).
III.1.5.2 - Sequence Integrity Mode
In the sequence integrity mode (SI = 1, bit located
in the Connection Memory), the input time slots
are put out 2 frames later (see Figure). In this
case, the delay is defined by a single expression:
So, the delay in sequence integrity mode varies
from 33 to 95 time slots.
III.1.6 - Connection Memory
III.1.6.1 - Description
The connection memory is composed of 256 loca-
tions addressed by the number of OTDM and TS
(8x32).
Each location permits:
– to connect each input time slot to one output
Three time slots if IMTD = 1, in this case n = 2 in
the formula hereafter or
two time slots if IMTD = 0, in this case n = 1 in
the same formula (see Paragraph “Switching
Matrix Configuration Register SMCR (0C)
time slot (If two or more output time slots are
connected to the same input time slot number,
there is broadcasting).
Constant Delay = (32 - ITSx) + 32 + OTSy
(OTDMi, TSj) ----> (ITDMi, TSj).
32 - (ITSx - OTSy) Time slots.
OTSy - ITSx + 32 Time slots
OTSy - ITSx Time slots
H
”).
– to select the variable delay mode or the se-
– to loop back an output time slot. In this case the
– to output the contents of the corresponding con-
– to output the sequence of the pseudo random
– to define the source of a sequence by the pseu-
– to assert a high impedance level on an output
– to deliver a programmable 256-bit sequence
III.1.6.2 - Access to Connection Memory
Supposing that the Switching Matrix Configuration
Register (SMCR) has been already written by the
microprocessor, it is possible to access to the con-
nection memory from microprocessor with the
help of two registers:
– Connection Memory Data Register (CMDR) and
– Connection Memory Address Register (CMAR).
III.1.6.3 - Access to Data Memory
To extract the contents of the data memory it is
possible to read the data memory from microproc-
essor with the help of the two registers:
– Connection Memory Data Register (CMDR) and
– Connection Memory Address Register (CMAR).
III.1.7 - Switching at 32 Kbit/s
Four TDMs can be programmed individually to
carry 64 channels at 32 Kbit/s (only if these TDMs
are at 2 Mbit/s).
Two bits (SW0/1) located in SMCR define the type
of channels of two couples of TDMs.
SW0 defines TDM0 and TDM4 (GCI0) and SW1
defines TDM1 and TDM5 (GCI1).
If TDM0 or/and TDM1 carry 64 channels at 32
quence integrity mode for any time slot.
contents of an input time slot (ITSx, ITDMp) is
the same as the output time slot (OTSx, OT-
DMp).
nection memory instead of the data which has
been stored in data memory.
sequence generator on an output time slot: a
pseudo random sequence can be inserted in
one or several time slots (hyperchannel) of the
same Output TDM; this insertion must be ena-
bled by the microprocessor in the configuration
register of the matrix.
do random sequence analyser: a pseudo ran-
dom sequence can be extracted from one or
several time slots (hyperchannel) of the same
Input TDM and routed to the analyser; this ex-
traction can be enabled by the microprocessor
in the configuration register of the matrix (SM-
CR).
time slot (disconnection).
during 125 microseconds on the Programmable
synchronization Signal pin (PSS).
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