STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 69

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For information:
T,S,R :
VI.43 - Initiate Block Address Register 2
This register concerns the second 32 HDLC Controller 2 named HDLC 2 connected to input6/output6 of
the switching matrix. The Interrupt Queue is common for the first HDLC Controller and for the second
HDLC Controller 2. So this register doesn’t concern the location of the Interrupt Queue.The location of the
Interrupt Queue is found from the contents of the first IBAR1 register (34)H.
A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the
The Initiate Block Address (IBA2) is:
The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.)
The least significant bit defines one of two bytes when the microprocessor selects one byte.
Example: MHDLC device address inside
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
bit15
23
A23
LT2
0
0
0
0
1
1
1
1
A22
external memory in the MHDLC address space).The offset is zero (A0 to A7 =”0”).
IBAR2 value = (310000 - 100000)/256 = 2100H
Initiate Block for HDLC2 address inside
tt
LT1
These three bits define the SDRAM circuit organisation (1word=2bytes))
0
0
1
1
0
0
1
1
T
0
0
0
0
1
1
1
1
A21
S
0
0
1
1
0
0
1
1
LT0
0
1
0
1
0
1
0
1
A20
R
0
1
0
1
0
1
0
1
NCAS latency
A19
(1Mx16) SDRAM circuit; shared RAM up to 4M words
(4Mx16) SDRAM circuit; shared RAM up to 8M words
(2Mx8) SDRAM circuit; shared RAM up to 8M words
(8Mx8) SDRAM circuit; shared RAM up to 8M words
R
R
R
R
R
1
2
3
A18
(and shared RAM organization)
SDRAM circuit organization
A17
P mapping = 100000H
After reset (0000)
A16
bit8
Reserved
Reserved
Reserved
Reserved
BL2
0
0
0
0
1
1
1
1
P mapping = 310000H
A15
bit7
BL1
0
0
1
1
0
0
1
1
H
A14
BL0
0
1
0
1
0
1
0
1
A13
Burst Length
A8
A12
8
Full page
WT=0
7
0
R
R
R
1
2
4
8
A11
2048 cycles / 32ms
4096 cycles / 64ms
4096 cycles / 64ms
4096 cycles / 64ms
0
0
If refresh
A10
0
Burst Length
0
IBAR2 (74)
STLC5466
A9
WT=1
0
R
R
R
R
1
2
4
8
69/130
0
bit0
A8
0
0
H