STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 61

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SWAP
VI.34 - Split Fetch Memory Register
This register must be programmed after reset before the first SDRAM access. Writing register is forbidden
between two SDRAM accesses.
FFA
NAB
bit15
A23
: Fast Fetch memory Access. This bit is taken into account only when synchronous 386EX micro-
: No Anticipation Burst
A22
The first byte (named 2b) of frames received (or transmitted) by the HDLCs is stored in bit 8/15
of the shared memory (or located in bit 8/15); the first bit received is stored in bit 8 of the shared
memory.
The first bit to be transmitted is located in bit 8 of the shared memory.
The second byte (named 2b+1) of the frame received (or transmitted) by the HDLCs is stored in
bit 0/7 of the shared memory; the first bit of the second byte received is stored in bit 0 of the
shared memory.
The ninth bit to be transmitted is located in bit 0 of the shared memory.
The bytes named (2b) are located in bit 8/15 of the shared memory; b from 0 to 2047.
The bytes named (2b+1) are located in bit 0/7of the shared memory.
SWAP=0
The first byte (named 2b) of frames received (or transmitted) by the HDLCs is stored in bit 0/7
of the shared memory (or located in bit 0/7); the first bit received is stored in bit 0 of the shared
memory.
The first bit to be transmitted is located in bit 0 of the shared memory.
The second byte (named 2b+1) of the frame received (or transmitted) by the HDLCs is stored in
processor is selected.
FFA = 1; in case of read from synchronous 386EX microprocessor
• if LBA delivered by the microprocessor is at”1”,
• if the word is already in the Fetch memory,
scribed above there is one Twait.
NAB = 1.
A read burst is generated only when a word required by the microprocessor is not present in the
fetch memory. No anticipation is done for potential further accesses.
fetch memory.
SWAP=1
bit 8/15 of the shared memory; the first bit of the second received is stored in bit 8 of the shared
memory.
The ninth bit to be transmitted is located in bit 8 of the shared memory.
The bytes named (2b) are located in bit 0/7 of the shared memory; b from 0 to 2047
The bytes named (2b+1) are located in bit 8/15 of the shared memory.
• if the Write FIFO is empty,
• if no current burst due to a previous read Access
then there is no Twait.
FFA = 0; in case of read from synchronous 386EX microprocessor with the same conditions de-
NAB = 0.
An anticipation is added to the fetch memory management.
If one of four words of a burst is read by the microprocessor in the fetch memory and
if the following four words are not present and valid in the fetch memory,
then the following four words are transferred automatically by anticipation from SDRAM to the
A21
A20
A19
A18
A17
After reset (0000)
A16
bit8
bit7
Nu
H
Nu
Nu
Nu
Nu
Nu
SFMR (4E)
STLC5466
NAB
61/130
FFA
bit0
H