XC3SD3400A-4CSG484LI Xilinx Inc, XC3SD3400A-4CSG484LI Datasheet - Page 99

• Manufacturer Part Number: XC3SD3400A-4CSG484LI
• Description: FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin BGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4CSG484LI

• Package: 484BGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 2322432
• Package / Case: 484-CSBGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 309
• Number Of Logic Elements/cells: 5968
• Number Of Gates: 3400000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Footprint Migration Differences
There are multiple migration footprint differences between the XC3SD1800A and the XC3SD3400A in the FG676 package.
These migration footprint differences are shown in
FG676 package to a Spartan-3A DSP device in the FG676 package is also possible. The XC3S1800A pin migration
differences have been added to
Table 70: FG676 Footprint Migration Differences
DS610 (v3.0) October 4, 2010
Product Specification
FG676
W25
W26
Ball
G16
G18
E20
D15
D19
B24
A23
A24
Y26
V26
U25
U26
H23
H24
H25
H26
G25
G26
B25
B26
F10
F18
D5
C4
F9
E6
E9
A5
A7
XC3S1400A
IP_L20N_1/
IP_L24N_1/
IP_L52N_1/
IP_L44P_1/
IP_L65P_1/
IP_L16N_1
IP_L48N_1
IP_L44N_1
IP_L65N_1
IP_L16P_1
IP_L20P_1
IP_L24P_1
IP_L48P_1
IP_L52P_1
VREF_1
VREF_1
VREF_1
VREF_1
VREF_1
Type
IP_0
N.C.
N.C.
IP_0
N.C.
N.C.
N.C.
IP_0
N.C.
IP_0
IP_0
IP_0
N.C.
IP_0
IP_0
IP_0
N.C.
Spartan-3A
XC3S1400A
Table 70
Bank
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
for designs migrating between these devices.
XC3SD1800A
IP_L20N_1/
IP_L24N_1/
IP_L52N_1/
IP_L44P_1/
IP_L65P_1/
IP_L16N_1
IP_L48N_1
IP_L44N_1
IP_L65N_1
IP_L16P_1
IP_L20P_1
IP_L24P_1
IP_L48P_1
IP_L52P_1
VREF_1
VREF_1
VREF_1
VREF_1
VREF_1
Type
Table
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
Spartan-3A DSP
www.xilinx.com
70. Migration from the XC3S1400A Spartan-3A device in the
XC3SD1800A
Bank
Spartan-3A DSP FPGA Family: Pinout Descriptions
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
XC3SD3400A
IP_1/VREF_1
IP_1/VREF_1
IP_1/VREF_1
IP_1/VREF_1
IP_1/VREF_1
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCO_0
VCCAUX
VCCAUX
VCCO_1
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IP_1
IP_1
Spartan-3A DSP
XC3SD3400A
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
0
1
1
1
1
1
1
1
1
FG676
W25
W26
Ball
G16
G18
D15
D19
A23
U25
U26
H23
H24
H25
H26
G25
G26
F10
F18
E20
B24
A24
Y26
V26
B25
B26
D5
C4
F9
E6
E9
A5
A7
99