XC3SD3400A-4CSG484LI Xilinx Inc, XC3SD3400A-4CSG484LI Datasheet - Page 58
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XC3SD3400A-4CSG484LI
Manufacturer Part Number
XC3SD3400A-4CSG484LI
Description
FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin BGA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheet
1.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD3400A-4CSG484LI
Package
484BGA
Family Name
Spartan®-3A
Device Logic Units
53712
Device System Gates
3400000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
309
Ram Bits
2322432
Package / Case
484-CSBGA
Mounting Type
Surface Mount
Voltage - Supply
1.1 V ~ 3.6 V
Operating Temperature
-40°C ~ 100°C
Number Of I /o
309
Number Of Logic Elements/cells
5968
Number Of Gates
3400000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD3400A-4CSG484LI
Manufacturer:
XILINX
Quantity:
108
Company:
Part Number:
XC3SD3400A-4CSG484LI
Manufacturer:
Xilinx Inc
Quantity:
10 000
Byte Peripheral Interface (BPI) Configuration Timing
X-Ref Target - Figure 14
(Open-Drain)
Table 54: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
DS610 (v3.0) October 4, 2010
Product Specification
T
T
T
T
T
T
T
T
CCLK1
CCLKn
MINIT
INITM
INITADDR
CCO
DCC
CCD
Symbol
PROG_B
LDC[2:0]
PUDC_B
CSO_B
A[25:0]
INIT_B
(Input)
(Input)
(Input)
(Input)
M[2:0]
D[7:0]
CCLK
HDC
Shaded values indicate specifications on attached parallel NOR Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on M[2:0] mode pins before the rising edge of INIT_B
Hold time on M[2:0] mode pins after the rising edge of INIT_B
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
Address A[25:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
Figure 14: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
T
MINIT
<0:1:0>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
Description
000_0000
T
CCLK1
Byte 0
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
T
INITADDR
000_0001
Byte 1
T
AVQV
Data
New ConfigRate active
Minimum
T
CCLK1
Address
T
50
CCO
0
0
5
Data
See T
T
DCC
See
See
See
SMDCC
T
Address
CCLKn
Maximum
Table 46
Table 46
Table 50
Data
in
–
–
5
–
Table 51
Address
DS529-3_05_090610
T
Data
CCD
T
cycles
Units
CCLK1
ns
ns
ns
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