XC3SD3400A-4CSG484LI Xilinx Inc, XC3SD3400A-4CSG484LI Datasheet - Page 74

• Manufacturer Part Number: XC3SD3400A-4CSG484LI
• Description: FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin BGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4CSG484LI

• Package: 484BGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 2322432
• Package / Case: 484-CSBGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 309
• Number Of Logic Elements/cells: 5968
• Number Of Gates: 3400000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS610 (v3.0) October 4, 2010
Product Specification
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
GCLK14
GCLK15
INPUT
INPUT
INPUT
L14N_0
L17P_0
L17P_2
L17P_2
L17N_2
L17N_2
L16P_2
L16N_2
GCLK4
GCLK0
GCLK0
GCLK1
GCLK1
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
12
I/O
I/O
I/O
I/O
I/O
I/O
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCO_2
VREF_2
L11P_0
L11N_0
L14P_0
L09N_0
L09P_0
L13N_0
L20P_2
L20P_2
L20N_2
L20N_2
INPUT
L21P_2
L18P_2
GCLK2
CSI B
CSI B
GND
GND
GND
GND
GND
MOSI
MOSI
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCO_0
VCCO_0
VCCO_2
VCCO_2
VREF_2
INPUT
INPUT
L10P_0
L12P_0
L13P_0
L25P_2
L25P_2
L21N_2
L18N_2
L19N_2
GCLK3
GND
GND
GND
GND
GND
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
VCCINT
VCCINT
VCCINT
VCCINT
VREF_0
VREF_2
VREF_2
INPUT
L10N_0
L12N_0
L08P_0
L05P_0
L05N_0
L25N_2
L25N_2
INPUT
INPUT
L24P_2
L24N_2
L19P_2
INPUT
INIT_B
GND
GND
GND
GND
GND
GND
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D3
2
2
Bank 0
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VREF_0
L06P_0
L08N_0
L04P_0
L04N_0
L29P_1
L13N_1
L28P_2
L28P_2
L28N_2
L28N_2
L29N_2
L22N_2
DOUT
GND
GND
GND
GND
GND
GND
GND
I/O
A16
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A3
Bank 2
Figure 16: CS484 Package Footprint (Top View–Right Half)
DIN/MISO
RHCLK7
RHCLK1
VREF_1
AWAKE
L06N_0
L03P_0
L03N_0
INPUT
INPUT
L34P_1
L26P_1
L29N_1
INPUT
L23N_1
L21N_1
L18N_1
L13P_1
INPUT
L12N_1
INPUT
L12P_1
L05N_1
L31N_2
L31N_2
L31P_2
L29P_2
L22P_2
L23P_2
GND
GND
GND
CCLK
CCLK
A14
A17
17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A2
D0
VCCAUX
VCCAUX
VCCAUX
VCCO_0
VREF_0
VCCO_1
VREF_1
RHCLK6
RHCLK0
VCCO_1
VREF_2
VCCO_2
INPUT
INPUT
INPUT
INPUT
L02P_0
L38N_1
L34N_1
L26N_1
L24N_1
L23P_1
L21P_1
L18P_1
L10N_1
L05P_1
L01P_1
L01P_1
L26P_2
L23N_2
IRDY1
HDC
HDC
I/O
A25
A15
I/O
I/O
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D2
2
VCCAUX
SUSPEN
SUSPEN
L07N_0
L02N_0
L01N_0
L36N_1
L15N_1
L01N_1
L01N_1
L26N_2
L27N_2
L01P_0
L38P_1
L30P_1
L32P_1
L24P_1
L10P_1
L07P_1
L03P_1
L27P_2
GND
GND
GND
LDC2
LDC2
A21
A24
A18
19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A7
A0
D1
D
D
RHCLK5
RHCLK3
VREF_1
INPUT
INPUT
INPUT
L07P_0
L36P_1
L35N_1
L30N_1
L31N_1
L32N_1
L25N_1
L25P_1
L20N_1
L19N_1
L15P_1
L16N_1
L07N_1
L09N_1
L09P_1
L09P_1
L03N_1
L03N_1
L04N_1
L30P_2
L30N_2
TRDY1
GND
GND
I/O
A20
A19
A13
A12
I/O
I/O
20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A6
A1
A1
0
VCCAUX
VCCAUX
VCCO_1
VCCO_1
RHCLK4
RHCLK2
VCCO_1
VCCO_1
VCCO_1
VREF_1
VREF_1
VREF_1
VREF_1
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INPUT
L39N_1
L37P_1
L35P_1
INPUT
L31P_1
INPUT
L27P_1
L20P_1
L19P_1
INPUT
L16P_1
INPUT
INPUT
L08N_1
L08N_1
INPUT
L04P_1
L02P_1
DONE
TCK
GND
GND
GND
LDC1
A22
21
I/O
I/O
I/O
I/O
I/O
VREF_1
VREF_1
INPUT
INPUT
INPUT
INPUT
L39P_1
L37N_1
L33N_1
L33P_1
L28N_1
L28P_1
L27N_1
L22N_1
L22P_1
L17N_1
L17P_1
L14N_1
L14P_1
L11N_1
L11P_1
L11P_1
L08P_1
L08P_1
L06P_1
L06N_1
L02N_1
GND
TDO
GND
LDC0
A23
A11
A10
I/O
22
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A9
A8
A5
A4
M
W
A
B
C
D
E
G
H
K
N
P
R
U
U
V
V
Y
A
A
A
B
F
J
L
T
Spartan-3A DSP FPGA Family: Pinout Descriptions
Right Half of CS484
Package (Top View)
74