XC3SD3400A-4CSG484LI Xilinx Inc, XC3SD3400A-4CSG484LI Datasheet - Page 84

• Manufacturer Part Number: XC3SD3400A-4CSG484LI
• Description: FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin BGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4CSG484LI

• Package: 484BGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 2322432
• Package / Case: 484-CSBGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 309
• Number Of Logic Elements/cells: 5968
• Number Of Gates: 3400000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

User I/Os by Bank
Table 67
AWAKE pin is counted as a dual-purpose I/O.
Table 67: User I/Os Per Bank for the XC3SD1800A in the FG676 Package
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
Top
Right
Bottom
Left
Package
TOTAL
28 VREF are on INPUT pins.
Edge
indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The
I/O Bank
0
1
2
3
Maximum I/Os
Input-Only
and
128
130
129
132
519
314
I/O
82
67
68
97
www.xilinx.com
INPUT
Spartan-3A DSP FPGA Family: Pinout Descriptions
28
15
21
18
82
All Possible I/O Pins by Type
DUAL
30
21
52
1
0
VREF
10
11
39
9
9
(1)
CLK
32
8
8
8
8
84