XC3SD3400A-4CSG484LI Xilinx Inc, XC3SD3400A-4CSG484LI Datasheet - Page 12

• Manufacturer Part Number: XC3SD3400A-4CSG484LI
• Description: FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin BGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4CSG484LI

• Package: 484BGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 2322432
• Package / Case: 484-CSBGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 309
• Number Of Logic Elements/cells: 5968
• Number Of Gates: 3400000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General DC Characteristics for I/O Pins
Table 8: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
3.
Symbol
I
I
R
R
RPU
RPD
I
R
I
C
I
PU
PD
REF
L
HS
DT
(2)
IN
The numbers in this table are based on the conditions set forth in
For single-ended signals that are placed on a differential-capable I/O, V
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
This parameter is based on characterization. The pull-up resistance R
(3)
(3)
(3)
(3)
Leakage current at User I/O,
Input-only, Dual-Purpose, and
Dedicated pins, FPGA powered
Leakage current on pins during
hot socketing, FPGA unpowered
Current through pull-up resistor
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins.
Dedicated pins are powered by
V
Equivalent pull-up resistor value
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on I
Current through pull-down
resistor at User I/O,
Dual-Purpose, Input-only, and
Dedicated pins
Equivalent pull-down resistor
value at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on I
V
Input capacitance
Resistance of optional
differential termination circuit
within a differential I/O pair. Not
available on Input-only pairs.
CCAUX
REF
current per pin
.
Description
RPU
RPD
per Note 2)
per Note 2)
V
Driver is in a high-impedance state,
V
All pins except INIT_B, PROG_B, DONE, and JTAG pins
when PUDC_B = 1.
INIT_B, PROG_B, DONE, and JTAG pins or other pins
when PUDC_B = 0.
V
CCAUX
IN
CCAUX
V
V
CCO
CCO
= 0V or V
V
V
V
= 2.25V to 2.75V
IN
IN
= 3.3V ± 10%
= 2.5V ± 10%
IN
= 3.0V to 3.6V
= GND
= V
= GND
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
CCO
CCO
www.xilinx.com
max, sample-tested
Test Conditions
All V
Table
PU
CCO
V
V
IN
7.
CCO
CCO
–
LVDS_33, MINI_LVDS_33,
LVDS_25, MINI_LVDS_25,
= V
V
of –0.2V to –0.5V is supported but can cause increased leakage
V
V
V
levels
CCAUX
V
V
V
V
V
V
V
V
CCO
CCO
CCAUX
CCO
or V
or V
V
V
V
V
V
V
V
V
IN
IN
CCO
CCO
CCO
CCO
CCO
CCO
IN
IN
IN
IN
IN
IN
IN
IN
= 1.14V to 1.26V
= 1.14V to 1.26V
/I
CCAUX
CCAUX
= 1.14V to 1.26V
= 1.14V to 1.26V
= 3.0V to 3.6V
= 2.3V to 2.7V
= 1.7V to 1.9V
= 1.4V to 1.6V
= 3.0V to 3.6V
= 2.3V to 2.7V
= 1.7V to 1.9V
= 1.4V to 1.6V
RSDS_33
RSDS_25
RPU
= 2.25V to 2.75V
= 1.7V to 1.9V
= 1.4V to 1.6V
= 3.0V to 3.6V
= 2.3V to 2.7V
= 1.7V to 1.9V
= 1.4V to 1.6V
= 3.0V to 3.6V
. The pull-down resistance R
= 3.0V to 3.6V
= 2.3V to 2.7V
(1)
–151
10.8
15.3
Min
–10
–10
–82
–36
–22
–11
167
100
–10
5.1
6.2
8.4
5.5
4.1
3.0
2.7
2.4
7.9
5.9
4.2
3.6
3.0
90
90
–
Add I
PD
–315
–182
HS
11.4
14.8
21.6
28.4
41.1
10.4
16.0
12.0
Typ
–88
–56
–31
346
225
100
110
7.8
5.7
5.1
4.5
8.5
7.2
6.0
–
–
–
–
= V
+ I
IN
RPU
119.4
/ I
–710
–437
–226
–148
Max
23.9
33.1
52.6
74.0
20.8
15.7
11.1
35.0
26.3
18.6
15.7
12.5
+10
+10
–83
659
457
+10
115
9.6
8.1
10
RPD
–
.
Units
µA
µA
µA
µA
µA
µA
µA
µA
kΩ
kΩ
kΩ
kΩ
kΩ
µA
µA
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
µA
pF
Ω
Ω
12