XC3S200AN-4FT256C Xilinx Inc, XC3S200AN-4FT256C Datasheet - Page 56

• Manufacturer Part Number: XC3S200AN-4FT256C
• Description: FPGA Spartan®-3AN Family 200K Gates 4032 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC3S200AN-4FT256C

• Package: 256FTBGA
• Family Name: Spartan®-3AN
• Device Logic Units: 4032
• Device System Gates: 200000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 195
• Ram Bits: 294912

Phase Shifter (PS)
Table 43: Recommended Operating Conditions for the PS in Variable Phase Mode
Table 44: Switching Characteristics for the PS in Variable Phase Mode
Miscellaneous DCM Timing
Table 45: Miscellaneous DCM Timing
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
Notes:
1.
2.
3.
Operating Frequency Ranges
PSCLK_FREQ (F
Input Pulse Requirements
PSCLK_PULSE
Phase Shifting Range
MAX_STEPS
FINE_SHIFT_RANGE_MIN
FINE_SHIFT_RANGE_MAX
DCM_RST_PW_MIN
DCM_RST_PW_MAX
DCM_CONFIG_LAG_TIME
The numbers in this table are based on the operating conditions set forth in
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
The DCM_DELAY_STEP values are provided at the bottom of
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
This specification is equivalent to the Virtex
FPGAs.
This specification is equivalent to the Virtex-4 FPGA T
Symbol
Symbol
Symbol
(2,3)
PSCLK
(2)
) Frequency for the PSCLK input
PSCLK pulse width as a percentage of the PSCLK period
(3)
Maximum allowed number of
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double
the clock effective clock period.
Minimum guaranteed delay for variable phase shifting
Maximum guaranteed delay for variable phase shifting
Minimum duration of a RST pulse width
Maximum duration of a RST pulse width
Maximum duration from V
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL
™
-4 FPGA DCM_RESET specification. This specification does not apply for Spartan-3AN
Description
Description
CONFIG
www.xilinx.com
Description
CCINT
Spartan-3AN FPGA Family: DC and Switching Characteristics
specification. This specification does not apply for Spartan-3AN FPGAs.
Table
applied to FPGA configuration
40.
CLKIN < 60 MHz [INTEGER(10 (T
CLKIN
Table 10

60 MHz [INTEGER(15 (T
and
40%
Table
Min
1
43.
-5
DCM_DELAY_STEP_MAX]
DCM_DELAY_STEP_MIN]
Phase Shift Amount
Max
60%
Speed Grade
167
[MAX_STEPS 
[MAX_STEPS 
Min
N/A
N/A
N/A
N/A
3
40%
Min
1
CLKIN
CLKIN
Max
-4
N/A
N/A
N/A
N/A
–
– 3 ns))]
– 3 ns))]
Max
60%
167
seconds
seconds
minutes
minutes
CLKIN
cycles
Units
Units
MHz
Units
steps
%
ns
ns
56