XC3S200AN-4FT256C Xilinx Inc, XC3S200AN-4FT256C Datasheet - Page 51
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XC3S200AN-4FT256C
Manufacturer Part Number
XC3S200AN-4FT256C
Description
FPGA Spartan®-3AN Family 200K Gates 4032 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S200AN-4FT256C
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S200AN-4FT256C
Manufacturer:
XILINX
Quantity:
302
Company:
Part Number:
XC3S200AN-4FT256C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Block RAM Timing
Table 38: Block RAM Timing
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
T
T
Hold Times
T
T
T
T
Clock Timing
T
T
Clock Frequency
F
RCKO
RCCK_ADDR
RDCK_DIB
RCCK_ENB
RCCK_WEB
RCKC_ADDR
RCKD_DIB
RCKC_ENB
RCKC_WEB
BPWH
BPWL
BRAM
Symbol
The numbers in this table are based on the operating conditions set forth in
When reading from block RAM, the delay from the active
transition at the CLK input to data appearing at the DOUT
output
Setup time for the ADDR inputs before the active transition at
the CLK input of the block RAM
Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM
Setup time for the EN input before the active transition at the
CLK input of the block RAM
Setup time for the WE input before the active transition at the
CLK input of the block RAM
Hold time on the ADDR inputs after the active transition at the
CLK input
Hold time on the DIN inputs after the active transition at the
CLK input
Hold time on the EN input after the active transition at the CLK
input
Hold time on the WE input after the active transition at the CLK
input
High pulse width of the CLK signal
Low pulse width of the CLK signal
Block RAM clock frequency
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table
0.32
0.28
0.69
1.12
1.56
1.56
Min
10.
–
0
0
0
0
0
-5
Max
2.06
320
Speed Grade
–
–
–
–
–
–
–
–
–
–
0.36
0.31
0.77
1.26
1.79
1.79
Min
–
0
0
0
0
0
-4
Max
2.49
280
–
–
–
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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