XC3S200AN-4FT256C Xilinx Inc, XC3S200AN-4FT256C Datasheet - Page 49

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XC3S200AN-4FT256C

Manufacturer Part Number
XC3S200AN-4FT256C
Description
FPGA Spartan®-3AN Family 200K Gates 4032 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC3S200AN-4FT256C

Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912

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Clock Buffer/Multiplexer Switching Characteristics
Table 36: Clock Distribution Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and
I1 inputs. Same as BUFGCE enable CE-input
Frequency of signals distributed on global buffers (all sides)
The numbers in this table are based on the operating conditions set forth in
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Symbol
F
T
T
BUFG
GIO
GSI
Table
10.
Minimum
0
0.22
0.56
350
-5
Speed Grade
Maximum
0.23
0.63
334
-4
Units
MHz
ns
ns
49

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