XC3S200AN-4FT256C Xilinx Inc, XC3S200AN-4FT256C Datasheet - Page 41
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XC3S200AN-4FT256C
Manufacturer Part Number
XC3S200AN-4FT256C
Description
FPGA Spartan®-3AN Family 200K Gates 4032 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S200AN-4FT256C
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S200AN-4FT256C
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XILINX
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Part Number:
XC3S200AN-4FT256C
Manufacturer:
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Quantity:
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Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions.
standard.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of V
High logic level of V
Some standards also require the application of a bias
voltage to the V
input-switching threshold. The measurement point of the
Input signal (V
and V
The Output test setup is shown in
voltage V
end of which is connected to the Output. For each standard,
R
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
Table 30: Test Methods for Timing Measurement at I/Os
DS557 (v4.1) April 1, 2011
Product Specification
Single-Ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
PCI66_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
T
and V
Signal Standard
H
(IOSTANDARD)
.
T
T
is applied to the termination resistor R
generally take on the standard values
Table 30
Rising
Falling
Rising
Falling
M
REF
) is commonly located halfway between V
H
pins of a given bank to properly set the
lists the conditions to use for each
is applied to the Input under test.
V
REF
0.75
1.25
1.25
0.9
0.9
0.9
1.1
0.9
0.9
1.5
1.5
–
–
–
–
–
–
–
–
Figure
(V)
11. A termination
V
V
V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Note
Note
V
Inputs
L
T
0
0
0
0
0
0
– 0.75
– 0.75
– 0.75
– 0.75
L
, the other
(V)
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
and a
3
3
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
L
V
V
V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Note
Note
V
LVCMOS, LVTTL), then R
open connection, and V
measurement point (V
used at the Output.
X-Ref Target - Figure 11
H
3.3
3.3
2.5
1.8
1.5
1.2
+ 0.75
+ 0.75
+ 0.75
+ 0.75
(V)
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
3
3
Notes:
1.
FPGA Output
Figure 11: Output Test Setup
The names shown in parentheses are
used in the IBIS file.
R
T
1M
1M
1M
1M
1M
1M
25
25
25
25
50
50
50
25
50
50
25
50
25
50
25
()
M
Outputs
T
) that was used at the Input is also
is set to zero. The same
T
V
is set to 1M to indicate an
T
(V
(2)
V
REF
R
C
0.75
1.25
1.25
T
3.3
3.3
1.5
0.9
0.9
1.8
0.9
0.9
1.5
1.5
T
L
0
0
0
0
0
0
0
0
(V)
(R
)
(C
V
DS312-3_04_102406
M
REF
REF
(V
)
MEAS
)
Inputs and
Outputs
)
V
V
V
V
V
V
V
V
V
V
V
V
1.65
1.25
0.75
0.94
2.03
0.94
2.03
M
1.4
0.9
0.6
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
(V)
41