XC3S200AN-4FT256C Xilinx Inc, XC3S200AN-4FT256C Datasheet - Page 119

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XC3S200AN-4FT256C

Manufacturer Part Number
XC3S200AN-4FT256C
Description
FPGA Spartan®-3AN Family 200K Gates 4032 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC3S200AN-4FT256C

Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912

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User I/Os by Bank
Table 83
The AWAKE pin is counted as a dual-purpose I/O.
Table 83: User I/Os Per Bank for the XC3S1400AN in the FGG676 Package
Footprint Migration Differences
The XC3S1400AN is the only Spartan-3AN FPGA offered in the FGG676 package. The XC3S1400AN FPGA is pin
compatible with the Spartan-3A XC3S1400A FPGA in the FG(G)676 package, although the Spartan-3A FPGA requires an
external configuration source.
DS557 (v4.1) April 1, 2011
Product Specification
Top
Right
Bottom
Left
Package
Edge
Total
indicates how the 502 available user-I/O pins are distributed between the four I/O banks on the FGG676 package.
I/O Bank
0
1
2
3
Maximum I/Os
120
130
120
132
502
313
I/O
82
67
67
97
www.xilinx.com
INPUT
20
15
14
18
67
All Possible I/O Pins by Type
Spartan-3AN FPGA Family: Pinout Descriptions
DUAL
30
21
52
1
0
VREF
10
10
38
9
9
CLK
32
8
8
8
8
119

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